AD9954SLASHPCBZ1 datasheet(23/40 Pages) AD

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AD9954

Rev. B | Page 23 of 40

Serial I/O Port

The AD9954 serial port is a flexible, synchronous, serial

communications port that easily interfaces to many industry-

standard microcontrollers and microprocessors. The serial I/O port

is compatible with most synchronous transfer formats, including

both the Motorola 6905/11 SPI® and Intel® 8051 SSR protocols.

The interface accesses all registers that configure the AD9954. MSB

first and LSB first transfer formats are supported. In addition, the

AD9954’s serial interface port can be configured as a single pin I/O

(SDIO), which allows a 2-wire interface, or two unidirectional pins

for in/out (SDIO/SDO), which enables a 3-wire interface. Two

optional pins, IOSYNC and CS, provide further flexibility for

system design with the AD9954.

SERIAL PORT OPERATION

With the AD9954, the instruction byte specifies read/write

operation and register address. Serial operations on the AD9954

only occur at the register level, they do not occur on the byte

level. For the AD9954, the serial port controller recognizes the

instruction byte register address and automatically generates the

proper register byte address. In addition, the controller expects

to access all bytes of that register. It is a requirement that all

bytes of a register be accessed during serial I/O operations, with

one exception; the IOSYNC function can be used to abort an

I/O operation, thereby allowing less than all bytes to be

accessed.

There are two phases to a communication cycle with the

AD9954. Phase 1 is the instruction cycle, which is the writing of

an instruction byte into the AD9954, coincident with the first

eight SCLK rising edges. The instruction byte provides the

AD9954 serial port controller with information regarding

Phase 2, the data transfer cycle. The instruction byte defines

whether the upcoming data transfer is a read or a write and the

serial address of the register being accessed.

The first eight SCLK rising edges of each communication cycle

are used to write the instruction byte into the AD9954. The

remaining SCLK edges are for Phase 2 of the communication

cycle. Phase 2 is the actual data transfer between the AD9954

and the system controller. The number of bytes transferred

during Phase 2 of the communication cycle is a function of the

Function Register 2, which is three bytes wide, Phase 2 requires that

three bytes be transferred. If accessing the frequency tuning word,

which is four bytes wide, four bytes must be transferred. After

transferring all data bytes per the instruction byte, the

communication cycle is complete.

At the completion of any communication cycle, the AD9954

serial port controller expects the next eight rising SCLK edges

to be the instruction byte of the next communication cycle. All

data input to the AD9954 is registered on the rising edge of

SCLK. All data is driven out of the AD9954 on the falling edge

of SCLK. Figure 25 through Figure 28 are provided to aid in

understanding the general operation of the AD9954 serial port.

INSTRUCTION CYCLE

SCLK

SDIO

DATA TRANSFER CYCLE

Figure 25. Serial Port Write Timing–Clock Stall Low

DON'T CARE

INSTRUCTION CYCLE

SCLK

SDIO

DATA TRANSFER CYCLE

DO 5 DO 4 DO 3 DO 2 DO 1

DO 0

DO 7 DO 6

SDO

Figure 26. 3-Wire Serial Port Read Timing–Clock Stall Low

INSTRUCTION CYCLE

SCLK

SDIO

DATA TRANSFER CYCLE

Figure 27. Serial Port Write Timing–Clock Stall High

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