AD9954SLASHPCBZ1 datasheet(15/40 Pages) AD

15 / 40 page

AD9954

Rev. B | Page 15 of 40

Clear-and-Release Function

When set for auto clearing, the corresponding accumulator is

cleared and then begins to accumulate again upon receipt of an

I/O update or change on one of the profile pins. This is repeated

for every subsequent I/O update or change on one of the profile

pins until the appropriate autoclear control bit is cleared. It is

perfectly valid to have one accumulator set to autoclearing and

the other set to continuous clear.

Amplitude Control Options

Shaped On-Off Keying

The shaped on-off keying function is enabled/disabled using

the OSK enable bit (CFR1<25>). This function allows the

user to control the ramp-up and ramp-down time when turning

the DAC on or off. This function is primarily used in burst

transmissions of digital data to reduce the adverse spectral

impact of short, abrupt bursts of data.

Both auto and manual shaped on-off keying modes are

supported. CFR1<24> is used to select between auto and

manual on-off keying modes. Figure 20 shows the block

diagram of the OSK circuitry.

Autoshaped On-Off Keying Mode Operation

When autoshaped on-off keying mode is enabled, a single-scale

factor is internally generated and applied to the multiplier input

for scaling the output of the DDS core block (see Figure 20). The

scale factor is the output of a 14-bit counter that increments/

decrements at a rate determined by the contents of the 8-bit

output ramp rate register. The scale factor increments if the

OSK pin is high and decrements if the OSK pin is low. The scale

factor is an unsigned value; all 0s multiply the DDS core output

by 0 (decimal), and 0x3FFF multiplies the DDS core output by

16,383 (decimal).

Table 6 details the increment/decrement step size of the

internally generated scale factor per the ASF<15:14> bits.

Note that the maximum amplitude allowed is limited by the

contents of the amplitude scale factor register, allowing the user

to ramp to a value less than full scale.

Table 6. Autoscale Factor Internal Step Size

ASF<15:14> (Binary)

Increment/Decrement Size

OSK Ramp Rate Timer

The OSK ramp rate timer is a loadable down counter, which

generates the clock signal to the 14-bit counter that generates

the internal scale factor. The ramp rate timer is loaded with

the value of the autoscale factor register (ASFR) every time

the counter reaches 1 (decimal). This load and countdown

operation continues for as long as the timer is enabled, unless

the timer is forced to load before reaching a count of 1.

If the load ARR control bit (CFR1<26>) is set, the ramp rate

timer is loaded upon an I/O update, upon a change in profile

input, or upon reaching a value of 1. The ramp timer can be

loaded before reaching a count of 1 by three methods.

The first method is by toggling the OSK pin or sending a rising

edge to the I/O UPDATE pin (or changing the state of a profile

pin). For this method, the ASFR value is loaded into the ramp

rate timer, which then proceeds to count down as normal.

The second method is if the load ARR control bit (CFR1<26>)

is set and an I/O update (or change in profile) is issued.

The last method is by setting the sweep enable bit. This switches

from inactive autoshaped on-off keying mode to the active

autoshaped on-off keying mode.

OSK PIN

LOAD OSK TIMER

CFR1<26>

SYNC_CLK

AUTO OSK

ENABLE

CFR1<24>

TO DAC

AUTOSCALE

FACTOR GENERATOR

RAMP RATE TIMER

CLOCK

DDS CORE

OSK ENABLE

CFR<25>

AMPLITUDE SCALE

FACTOR REGISTER

(ASF)

HOLD

INC/DEC ENABLE

OUT

COS(X)

AMPLITUDE RAMP

RATE REGISTER

(ASF)

UP/DN

DATA

LOAD

Figure 20. On-Off Shaped Keying, Block Diagram

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