AD9954SLASHPCBZ1 datasheet(19/40 Pages) AD

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AD9954

Rev. B | Page 19 of 40

FTW0

SINGLE-TONE

MODE

LINEAR SWEEP MODE

AT POINT A: LOAD RISING RAMP RATE REGISTER, APPLY RISING DFTW.

AT POINT B: LOAD FALLING RAMP RATE REGISTER, APPLY FALLING DFTW.

PS<0> = 1

PS<0>= 0

PS<0> =0

TIME

FTW1

fOUT

Figure 21. Linear Sweep Frequency Plan

FTW0

SINGLE-TONE

MODE

LINEAR SWEEP MODE ENABLE–NO DWELL BIT SET

FTW1

fOUT

TIME

PS<0> = 1 PS<0> = 0

PS<0> = 0

PS<0> = 1

PS<0> = 0

Figure 22. Linear Sweep Using No-Dwell Frequency Plan

Linear Sweep No-Dwell Feature

See CFR1<2> in the register maps (see Table 12 and Table 13)

for general details of the no-dwell mode. Figure 22 depicts the

linear sweep mode operation when the linear sweep no-dwell

bit is set. The Label A points indicate where a rising edge on

PS0 is detected; the Label B points indicate where the AD9954

has determined fOUT has reached the terminal frequency and

automatically returns to the starting frequency. Note that in this

mode, only sweeps from FTW0 to FTW1 using the positive

linear sweep control word are supported. Toggling PS0 from 1

to 0 neither initiates a falling sweep when the no-dwell bit is set,

nor interrupts a positive sweep already underway.

Resetting the Ramp Rate Timer

The ramp timer can be reset before reaching a count of 1 by

three methods.

Method one is by changing the PS0 input pin. When the PS0

input pin toggles from 0 to 1, the RSRRW value is loaded into

the ramp rate timer, which then proceeds to countdown as

normal. When the PS0 input pin toggles from 0 to 1, the falling

sweep ramp rate word (FSRRW) value is loaded into the ramp

rate timer, which then proceeds to countdown as normal.

The second method uses the LOAD SRR @ I/O UD bit

(CFR1<15>), see Table 12 for details.

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