AD9954SLASHPCBZ1 datasheet(14/40 Pages) AD

14 / 40 page

AD9954

Rev. B | Page 14 of 40

Comparator

Some applications (for example, clocking) prefer a square-wave

signal rather than a sine wave. In support of such applications,

the AD9954 includes an on-chip comparator. The comparator

has a bandwidth greater than 200 MHz and a common-mode

input range of 1.3 V to 1.8 V. The comparator can be turned off

to reduce power consumption using the comparator power-

down bit, CFR1<6>.

Frequency Accumulator

This block is used for linear sweep mode; transitioning from

the start frequency (F0) to the terminal frequency (F1) is not

instantaneous but instead is implemented in a swept or ramped

fashion. This frequency ramping is accomplished by stepping

through intermediate frequencies between F0 and F1.

The linear sweep block uses the falling and rising delta

frequency tuning words, the falling and rising delta frequency

ramp rates, and the frequency accumulator. The Linear Sweep

Enable Bit CFR1<21> enables the linear sweep block. The linear

sweep no dwell bit establishes the action to be performed upon

reaching the terminal frequency in a sweep. See the Modes of

Operation section for more details.

DDS Core

The output frequency (fO) of the DDS is a function of the

frequency of system clock (SYSCLK), the value of the frequency

tuning word (FTW), and the capacity of the phase accumulator

(232, in this case). The exact relationship is given below with fs

defined as the frequency of SYSCLK.

= (FTW)(fS)/232 with 0 ≤ FTW ≤ 231

= fS × (1 − (FTW/232)) with 231 < FTW < 232 − 1

Each system clock cycle, the FTW is added to the value

previously held in the phase accumulator. The value at the

output of the phase accumulator is then summed with a user-

defined, 14-bit phase offset value (POW). The most significant

19 bits of that summation are then translated to an amplitude

value via the cos(x) functional block. Truncation of the LSBs is

implemented to reduce the power consumption of the DDS

core. This truncation does not reduce frequency resolution.

In certain applications, it is desirable to have the ability to force

the output signal to zero phase. Simply setting the FTW to 0

does not accomplish this; it only stalls the core at its current

phase value. A control bit is provided to force the phase

accumulator output to zero.

At power-up, the clear phase accumulator bit is set to Logic 1,

but the buffer memory for this bit is cleared (Logic 0). Therefore,

upon power-up, the phase accumulator remains clear until the

first I/O UPDATE is issued. I/O UPDATE transfers data from

the input buffers to the active control registers. See the

Functionality of the SYNC_CLK and I/O UPDATE section

for more details.

Frequency Tuning Word Mux

As shown in Figure 2, there are three sources for the FTW

that are fed to the DDS core as the seed value for the phase

accumulator: a frequency accumulator, the static RAM, and

the registers of the control logic.

For applications where a static output frequency or more than

four predefined output frequencies need to be switched between,

in some variable or undefined order, the primary method of

setting the FTW is by programming the desired value into the

FTW0 register.

For applications where up to four specific sets of FTWs, or pre-

defined series of FTWs are needed, the on-board RAM can be

programmed with the desired FTWs, and the profile pins can

be used to toggle between those sets/series.

For applications where a steady sweeping of frequency is

desired, a second frequency accumulator is provided. The seed

value and minimum/maximum numbers for the frequency

accumulator are user programmable, although certain rules

must be followed to avoid overflowing that accumulator.

Phase Offset Word Mux

As shown in Figure 2, there are two sources for the POW that

are fed to the DDS core as an adder to the output of the phase

accumulator: the static RAM and the registers of the control

logic. Using this feature enables synchronization of the DDS

output to other system signals as well as phase modulation.

For applications where a static output phase or more than four

predefined output phases need to be switched between, in some

variable or undefined order, the primary method of setting the

POW is by programming the desired value into the POW0

For applications where up to four specific sets of POWs, or

predefined series of POWs are needed, the on-board RAM can

be programmed with the desired POWs, and the profile pins

can be used to toggle between those sets/series.

The phase offset formula is





















360

POW

A digital delay block exists in the phase offset programming

path to ensure matched latency with changes to the frequency

tuning word. This enables users to easily program the device to

change from one combined phase/frequency combination to

another smoothly and seamlessly.

Continuous and Clear-and-Release Frequency and Phase

Accumulator Clear Functions

The AD9954 allows for a continuous zeroing of the frequency

sweep logic and the phase accumulator as well as a clear and

release or automatic zeroing function. The auto clear bits are

CFR1<14:13>. The continuous clear bits are CFR1<11:10>.

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