AD7416ARMZ datasheet(14/24 Pages) AD

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AD7416/AD7417/AD7418

Rev. I | Page 14 of 24

ANALOG INPUT

0V 1/2LSB

111...111

111...110

111...000

011...111

000...010

000...001

000...000

+VREF – 1LSB

1LSB – VREF/1024

Figure 14. Ideal Transfer Function Characteristic for the AD7417/AD7418

Config2 Register (Address 0x05)

A second configuration register is included in the AD7417/

AD7418 for the functionality of the CONVST pin. It is an 8-bit

whether the AD7417/AD7418 should be operated in its default

mode (D7 = 0), performing conversions every 355 μs or in its

CONVST pin mode (D7 = 1), where conversions start only

when the CONVST pin is used. Bit 6 contains the Test 1 bit.

When this bit is 0, the I2C filters are enabled (default). Setting

this bit to 1 disables the filters.

Table 16. Config2 Register

Conversion mode

Test 1

SERIAL BUS INTERFACE

Control of the AD7416/AD7417/AD7418 is carried out via the

I2C compatible serial bus. The AD7416/AD7417/AD7418 are

connected to this bus as a slave device, under the control of a

master device, for example, the processor.

Serial Bus Address

As with all I2C compatible devices, the AD7416/AD7417/AD7418

have a 7-bit serial address. The four MSBs of this address for the

AD7416 are set to 1001; the AD7417 are set to 0101, and the

three LSBs can be set by the user by connecting the A2 to A0

pins to either VDD or GND. By giving them different addresses,

up to eight AD7416/AD7417 devices can be connected to a

single serial bus, or the addresses can be set to avoid conflicts

with other devices on the bus. The four MSBs of this address for

the AD7418 are set to 0101, and the three LSBs are all set to 0.

If a serial communication occurs during a conversion operation,

the conversion stops and restarts after the communication.

The serial bus protocol operates as follows:

The master initiates data transfer by establishing a start condi-

tion, defined as a high-to-low transition on the serial data

line, SDA, while the serial clock line, SCL, remains high.

This indicates that an address/data stream follows. All slave

peripherals connected to the serial bus respond to the 7-bit

address (MSB first) plus an R/W bit, which determines the

direction of the data transfer, that is, whether data is written

to or read from the slave device.

The peripheral whose address corresponds to the transmitted

address responds by pulling the data line low during the low

period before the ninth clock pulse, known as the acknowl-

edge bit. All other devices on the bus now remain idle while

the selected device waits for data to be read from or written

to it. If the R/W bit is a 0, then the master writes to the

slave device. If the R/W bit is a 1, then the master reads

from the slave device.

Data is sent over the serial bus in sequences of nine clock

pulses, eight bits of data followed by an acknowledge bit

from the receiver of data. Transitions on the data line must

occur during the low period of the clock signal and remain

stable during the high period, because a low-to-high transi-

tion when the clock is high may be interpreted as a stop signal.

When all data bytes have been read or written, stop

conditions are established. In write mode, the master pulls

the data line high during the 10th clock pulse to assert a

stop condition. In read mode, the master device pulls the

data line high during the low period before the ninth clock

pulse. This is known as no acknowledge. The master then

takes the data line low during the low period before the

10th clock pulse, then high during the 10th clock pulse to

assert a stop condition.

Any number of bytes of data can be transferred over the serial

bus in one operation, but it is not possible to mix read and write

in one operation because the type of operation is determined at

the beginning and cannot subsequently be changed without

starting a new operation.

Writing to the AD7416/AD7417/AD7418

Depending on the register being written to, there are three

different writes for the AD7416/AD7417/AD7418.

•

Writing to the address pointer register for a subsequent read.

To read data from a particular register, the address pointer

not, the correct address must be written to the address pointer

in Figure 15. The write operation consists of the serial bus

address followed by the address pointer byte. No data is

written to any of the data registers.

•

Writing a single byte of data to the configuration register, the

Config2 register, or to the TOTI setpoint or THYST setpoint

registers.

The configuration register is an 8-bit register, so only one

byte of data can be written to it. If only 8-bit temperature

comparisons are required, the temperature LSB can be

ignored in TOTI and THYST, and only eight bits need to be

written to the TOTI setpoint and THYST setpoint registers.

Writing a single byte of data to one of these registers consists

of the serial bus address, the data register address written

to the address pointer register, followed by the data byte

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