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AD5322ARMZ датащи(PDF) 16 Page - Analog Devices

номер детали AD5322ARMZ
подробное описание детали  2.5 V to 5.5 V, 230 關A, Dual Rail-to-Rail, Voltage Output 8-/10-/12-Bit DACs
PDF  24 Pages
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производитель  AD [Analog Devices]
домашняя страница  http://www.analog.com
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AD5322ARMZ датащи(HTML) 16 Page - Analog Devices

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AD5302/AD5312/AD5322
Rev. D | Page 16 of 24
POWER-DOWN MODES
The AD5302/AD5312/AD5322 have very low power consump-
tion, dissipating only 0.7 mW with a 3 V supply and 1.5 mW
with a 5 V supply. Power consumption can be further reduced
when the DACs are not in use by putting them into one of three
power-down modes, which are selected by Bit 13 and Bit 12
(PD1 and PD0) of the control word. Table 7 shows how the
state of the bits corresponds to the mode of operation of that
particular DAC.
Table 7. PD1/PD0 Operating Modes
PD1
PDO
Operating Mode
0
0
Normal Operation
0
1
Power-Down (1 kΩ Load to GND)
1
0
Power-Down (100 kΩ Load to GND)
1
1
Power-Down (High Impedance Output)
When both bits are set to 0, the DACs work normally with
their normal power consumption of 300 μA at 5 V. However,
for the three power-down modes, the supply current falls to
200 nA at 5 V (50 nA at 3 V). Not only does the supply current
drop, but the output stage is also internally switched from the
output of the amplifier to a resistor network of known values.
This has the advantage that the output impedance of the part is
known while the part is in power-down mode and provides a
defined input condition for whatever is connected to the output
of the DAC amplifier. There are three different options.
The output is connected internally to GND through a
1 kΩ resistor,
The output is connected internally to GND through a
100 kΩ resistor, or
The output is left open-circuited (three-state).
The output stage is illustrated in Figure 33.
The bias generator, the output amplifier, the resistor string,
and all other associated linear circuitry are shut down when
the power-down mode is activated. However, the contents of
the registers are unaffected when in power-down. The time to
exit power-down is typically 2.5 μs for VDD = 5 V and 5 μs when
VDD = 3 V. See Figure 23 for a plot.
RESISTOR-
STRING DAC
AMPLIFIER
VOUT
POWER-DOWN
CIRCUITRY
RESISTOR
NETWORK
Figure 33. Output Stage During Power-Down



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