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AD5322ARMZ датащи(PDF) 5 Page - Analog Devices

номер детали AD5322ARMZ
подробное описание детали  2.5 V to 5.5 V, 230 關A, Dual Rail-to-Rail, Voltage Output 8-/10-/12-Bit DACs
PDF  24 Pages
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производитель  AD [Analog Devices]
домашняя страница  http://www.analog.com
Logo AD - Analog Devices

AD5322ARMZ датащи(HTML) 5 Page - Analog Devices

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AD5302/AD5312/AD5322
Rev. D | Page 5 of 24
TIMING CHARACTERISTICS
VDD = 2.5 V to 5.5 V, all specifications TMIN to TMAX, unless otherwise noted.1, 2, 3
Table 3.
Parameter
Limit at TMIN, TMAX (A, B Version)
Unit
Conditions/Comments
t1
33
ns min
SCLK Cycle Time
t2
13
ns min
SCLK High Time
t3
13
ns min
SCLK Low Time
t4
0
ns min
SYNC to SCLK Active Edge Setup Time
t5
5
ns min
Data Setup Time
t6
4.5
ns min
Data Hold Time
t7
0
ns min
SCLK Falling Edge to SYNC Rising Edge
t8
100
ns min
Minimum SYNC High Time
t9
20
ns min
LDAC Pulse Width
t10
20
ns min
SCLK Falling Edge to LDAC Rising Edge
1 Guaranteed by design and characterization, not production tested.
2 All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.
3 See Figure 2.
SCLK
DIN1
DB15
DB0
1SEE INPUT SHIFT REGISTER SECTION.
t1
t3
t2
t7
t9
t10
t5
t4
t6
t8
LDAC
LDAC
SYNC
Figure 2. Serial Interface Timing Diagram



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