PIC24FJ256GA110_10 datasheet(59/330 Pages) MICROCHIP

59 / 330 page

 2010 Microchip Technology Inc.

DS39905E-page 59

PIC24FJ256GA110 FAMILY

NVMCON: FLASH MEMORY CONTROL REGISTER

R/SO-0(1)

R/W-0(1)

U-0

WREN

WRERR

—

bit 15

bit 8

U-0

R/W-0(1)

U-0

R/W-0(1)

—ERASE

—

—NVMOP3(2)

NVMOP2(2)

NVMOP1(2)

NVMOP0(2)

bit 7

bit 0

Legend:

SO = Set Only bit

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 15

WR:

Write Control bit(1)

= Initiates a Flash memory program or erase operation. The operation is self-timed and the bit is

cleared by hardware once the operation is complete.

= Program or erase operation is complete and inactive

bit 14

WREN:

Write Enable bit(1)

= Enable Flash program/erase operations

= Inhibit Flash program/erase operations

bit 13

WRERR:

Write Sequence Error Flag bit(1)

= An improper program or erase sequence attempt or termination has occurred (bit is set

automatically on any set attempt of the WR bit)

= The program or erase operation completed normally

bit 12-7

Unimplemented:

Read as ‘0’

bit 6

ERASE:

Erase/Program Enable bit(1)

= Perform the erase operation specified by NVMOP<3:0> on the next WR command

= Perform the program operation specified by NVMOP<3:0> on the next WR command

bit 5-4

Unimplemented:

Read as ‘0’

bit 3-0

NVMOP<3:0>:

NVM Operation Select bits(1,2)

1111

= Memory bulk erase operation (ERASE = 1) or no operation (ERASE = 0)(3)

0011

= Memory word program operation (ERASE = 0) or no operation (ERASE = 1)

0010

= Memory page erase operation (ERASE = 1) or no operation (ERASE = 0)

0001

= Memory row program operation (ERASE = 0) or no operation (ERASE = 1)

Note 1:

These bits can only be reset on POR.

All other combinations of NVMOP<3:0> are unimplemented.

Available in ICSP™ mode only. Refer to the device programming specification.

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