MPC950 MPC951

TIMING SOLUTIONS

BR1333 — Rev 6

11

MOTOROLA

be driven by each output of the MPC950/951 clock driver. For

the series terminated case however there is no DC current

draw, thus the outputs can drive multiple series terminated

lines. Figure 12 illustrates an output driving a single series

terminated line vs two series terminated lines in parallel.

When taken to its extreme the fanout of the MPC950/951

clock driver is effectively doubled due to its capability to drive

multiple lines.

Figure 12. Single versus Dual Transmission Lines

7

Ω

IN

MPC950/951

OUTPUT

BUFFER

RS = 43Ω

ZO = 50Ω

OutA

7

Ω

IN

MPC950/951

OUTPUT

BUFFER

RS = 43Ω

ZO = 50Ω

OutB0

RS = 43Ω

ZO = 50Ω

OutB1

The waveform plots of Figure 13 show the simulation

results of an output driving a single line vs two lines. In both

cases the drive capability of the MPC950/951 output buffers

is more than sufficient to drive 50

Ω transmission lines on the

incident edge. Note from the delay measurements in the

simulations a delta of only 43ps exists between the two

differently loaded outputs. This suggests that the dual line

driving need not be used exclusively to maintain the tight

output–to–output skew of the MPC950/951. The output

waveform in Figure 13 shows a step in the waveform, this

step is caused by the impedance mismatch seen looking into

the driver. The parallel combination of the 43

Ω series resistor

plus the output impedance does not match the parallel

combination of the line impedances. The voltage wave

launched down the two lines will equal:

VL = VS ( Zo / (Rs + Ro +Zo))

Zo = 50

Ω || 50Ω

Rs = 43

Ω || 43Ω

Ro = 7

Ω

VL = 3.0 (25 / (21.5 + 7 + 25) = 3.0 (25 / 53.5)

= 1.40V

At the load end the voltage will double, due to the near

unity reflection coefficient, to 2.8V. It will then increment

towards the quiescent 3.0V in steps separated by one round

trip delay (in this case 4.0ns).

Figure 13. Single versus Dual Waveforms

TIME (nS)

3.0

2.5

2.0

1.5

1.0

0.5

0

2

4

6

8

10

12

14

OutB

tD = 3.9386

OutA

tD = 3.8956

In

Since this step is well above the threshold region it will not

cause any false clock triggering, however designers may be

uncomfortable with unwanted reflections on the line. To

better match the impedances when driving multiple lines the

situation in Figure 14 should be used. In this case the series

terminating resistors are reduced such that when the parallel

combination is added to the output buffer impedance the line

impedance is perfectly matched.

Figure 14. Optimized Dual Line Termination

7

Ω

MPC950/951

OUTPUT

BUFFER

RS = 36Ω

ZO = 50Ω

RS = 36Ω

ZO = 50Ω

7

Ω + 36Ω k 36Ω = 50Ω k 50Ω

25

Ω = 25Ω

SPICE level output buffer models are available for

engineers who want to simulate their specific interconnect

schemes. In addition IV characteristics are in the process of

being generated to support the other board level simulators in

general use.