MPC950 MPC951

TIMING SOLUTIONS

BR1333 — Rev 6

7

MOTOROLA

MPC950

Figure 1. Dual Frequency Configuration

fsela

‘1’

fselb

‘1’

fselc

‘1’

fseld

‘0’

Input Ref

16.66MHz

66.66MHz

Qa

33.33MHz

Qb

33.33MHz

Qc

1

1

2

MPC950

Figure 2. Dual Frequency Configuration

‘1’

‘0’

‘0’

‘1’

Input Ref

33.33MHz

66.66MHz

Qa

66.66MHz

Qb

66.66MHz

Qc

1

1

2

FBsel

‘0’

FBsel

‘1’

fsela

fselb

fselc

fseld

66.66MHz

Qd

5

33.33MHz

Qd

5

MPC950

Figure 3. Dual Frequency Configuration

fsela

‘1’

fselb

‘1’

fselc

‘1’

fseld

‘1’

Input Ref

16.66MHz

66.66MHz

Qa

33.33MHz

Qb

33.33MHz

Qc

1

1

2

MPC950

Figure 4. Triple Frequency Configuration

‘0’

‘0’

‘1’

‘1’

Input Ref

20MHz

160MHz

Qa

80MHz

Qb

40MHz

Qc

1

1

2

FBsel

‘0’

FBsel

‘0’

fsela

fselb

fselc

fseld

33.33MHz

Qd

5

40MHz

Qd

5

MPC951

‘1’

‘0’

‘0’

‘0’

Input Ref

75MHz

Ext_FB

1

MPC951

‘0’

‘0’

‘0’

‘1’

Input Ref

25MHz

Ext_FB

1

fsela

fselb

fselc

fseld

fsela

fselb

fselc

fseld

75MHz

Qa

75MHz

Qb

75MHz

Qc

1

1

2

75MHz

Qd

5

Figure 5. “Zero” Delay Buffer

Figure 6. “Zero” Delay Frequency Multiplier

1

100MHz

Qa

50MHz

Qb

50MHz

Qc

1

1

2

25MHz

Qd

5

Jitter Performance of the MPC950/951

With the clock rates of today’s digital systems continuing

to increase more emphasis is being placed on clock

distribution design and management. Among the issues

being addressed is system clock jitter and how that affects

the overall system timing budget. The MPC950/951 was

designed to minimize clock jitter by employing a differential

bipolar PLL as well as incorporating numerous power and

ground pins in the design. The following few paragraphs will

outline the jitter performance of the MPC950/951, illustrate

the measurement limitations and provide guidelines to

minimize the jitter of the device.

The most commonly specified jitter parameter is

cycle–to–cycle jitter. Unfortunately with today’s high

performance measurement equipment there is no way to

measure this parameter for jitter performance in the class

demonstrated by the MPC950/951. As a result different

methods are used which approximate cycle–to–cycle jitter.

The typical method of measuring the jitter is to accumulate a

large number of cycles, create a histogram of the edge

placements and record peak–to–peak as well as standard

deviations of the jitter. Care must be taken that the measured

edge is the edge immediately following the trigger edge. If

this is not the case the measurement inaccuracy will add

significantly to the measured jitter. The oscilloscope cannot

collect adjacent pulses, rather it collects data from a very

large sample of pulses. It is safe to assume that collecting

pulse information in this mode will produce jitter values

somewhat larger than if consecutive cycles were measured,

therefore, this measurement will represent an upper bound of

cycle–to–cycle jitter. Most likely, this is a conservative

estimate of the cycle–to–cycle jitter.

There are two sources of jitter in a PLL based clock driver,

the commonly known random jitter of the PLL and the less

intuitive jitter caused by synchronous, different frequency

outputs switching. For the case where all of the outputs are