ADP3801/ADP3802

–11–

REV. 0

ADP3800

COMP

EOC

(a) EOC Output Terminates Charge

270

2N3906

ADP3800

EOC

VL

100k

0.1 F

(b) EOC Turns on LED to Signal Charge Completion

2N3904

2

ADP3800

EOC

VL

COMP

100k

100k

2N3906

0.1 F

10k

20k

20k

270

(c) EOC Terminates Charge and Turns on LED

100k

ADP3800

EOC

*LEVEL SHIFTED TO

TO DRIVE PMOS

VL

100k

100k

2N3906

1 F

COMP

RESET

J

K

Q

Q

74H73A

BATSELB*

A/B + BATSELA*

100k

0.1 F

20k

2N3904

2

10k

(d) Flip-Flop Switches Between Batteries on EOC Signal

Figure 23. EOC Output Circuits

COMP Node

Both the current loop and the voltage loop share a common,

high impedance compensation node, labeled COMP. A series

capacitor and resistor on this node help to compensate both

loops. The resistor is included to provide a zero in the loop

response and boost phase margin.

The voltage at the COMP node determines the duty cycle of the

PWM. The threshold levels are typically 1.0 V for 0% duty cycle

and 2.0 V for 100% duty cycle, resulting in a total range of

1.0 V. When the ADP3801/ADP3802 first turns on, the COMP

capacitor is at 0.0 V. It has to charge up to at least 1.0 V before

the duty cycle rises above 0% and the pass transistor turns on.

This “soft-start” behavior is desirable to avoid undue stress on

the external components. In addition, whenever the part is

placed in Shutdown or in UVLO, the COMP capacitor is dis-

charged to ensure soft start upon recovery.

The current available to charge and discharge the COMP ca-

pacitor during normal operation is 100

µA. Thus, the slew rate

at this node is equal to 100

µA divided by the capacitor. For a

typical capacitance of 1

µF, the slew rate is 0.1 V/ms. Thus, it

takes about 10 ms before the ADP3801/ADP3802 starts to

operate from a soft-start state. This is regardless of the internal

oscillator frequency. One important note is that the COMP

node is a high impedance point. Any external resistance or leak-

age current on this node will cause an error in both the charge

current control and the final battery voltage.

Gate Drive

The ADP3801/ADP3802 gate drive is designed to provide high

transient currents to drive the pass transistor. The rise and fall

times are typically 20 ns and 200 ns respectively when driving

60 m

Ω. Figure 15 shows the typical transient response of the

output stage driving this load from a 10 V supply.

A voltage clamp is added to limit the pull-down voltage to 7 V

below VCC. For example, if VCC is 10 V then the output will

the external FET.

Low Dropout Regulator and Reference

A 3.3 V LDO is used to generate a regulated supply for internal

circuitry. Additionally, the LDO can deliver up to 10 mA of

current to power external circuitry such as a microcontroller. A

1.0

µF capacitor must be placed close to the VL pin to ensure

stability of the regulator. Due to the design of the regulator,

stability is not contingent on the ESR for the output capacitor.

Many different types of capacitors can be used providing flex-

ibility and ease of design. The LDO also includes a high accu-

racy, low drift internal reference equal to half of VL to set levels

within the part. During shutdown and UVLO, both the refer-

ence and the LDO remain active.

Shutdown

The IC may be placed in shutdown at any time to stop charging

of the batteries and to conserve power. For example, to safely

switch from one battery to the next, the part should be shut

down to momentarily interrupt charging. Also, if the batteries

have completed charging or no batteries are present, then the

part may be placed in shutdown to save power. A logic low on