REV. 0

ADMCF340

–33–

PORTA_DIR (R/W)

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

15

14

13

12

11

10

98

7654

321

0

PA0-PA8

DM (0x2004)

0 = INPUT

1 = OUTPUT

PORTB_DIR (R/W)

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

15

14

13

12

11

10

98

76

54

3

210

PB0-PB15

DM (0x2044)

(NOT USED IN ADMCF341)

0 = INPUT

1 = OUTPUT

PORTA_DATA (R/W)

0

0

0

0

15

14

13

12

11

10

98765432

10

0

0

0

0

PA0-PA8

DM (0x2005)

0 = LOW LEVEL

1 = HIGH LEVEL

00

000

000

PORTB_DATA (R/W)

15

14

13

12

11

10

98

76

54321

0

PB0-PA15

DM (0x2045)

(NOT USED IN ADMCF341)

0 = LOW LEVEL

1 = HIGH LEVEL

000

000

000

000

0

000

PORTA_SELECT (R/W)

0

0

0

0

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

1

0

0

0

1

1

1

11

1

1

1

0 = DR0

1 = PA0

0 = DT0

1 = PA1

0 = RFS0

1 = PA2

0 = TFS0

1 = PA3

0 = AUX0/CLOCKOUT

1 = PA8

0 = AUX1/PWMSYNC

1 = PA7

0 = DR1

1 = PA6

0 = SCLK1/SCLK0

1 = PA4

0 = PWMSYNC

1 = AUX1

0 = DT1/FL1

1 = PA5

0 = CLOCKOUT

1 = AUX0

DM (0x2049)

Figure 24. Configuration of PIO Registers

Default bit values are shown; if no value is shown, the bit field is undefined at reset. Reserved bits are shown on a gray field—these

bits should always be written as shown.