ADMCF340BST datasheet(16/40 Pages) AD

16 / 40 page

REV. 0

ADMCF340

–16–

In general, the on-times of the PWM signals in double update

mode are deﬁned by:

TAH = (PWMCHA1 + PWMCHA2 – PWMDT1 – PWMDT2 )

× TCK

TAL = (PWMTM1 + PWMTM2 – PWMCHA1 – PWMCHA2 –

PWMDT1 – PWMDT2)

× TCK

PWMCHA

PWMTM

PWMDT

PWMTM

PWMCHA

PWMTM

PWMCHA

PWMDT

PWMTM

−

()

–

because of the completely general case in double update mode,

the switching period is given by:

PWNMTM

PWMTM

SCK

() ×

Again, the values of TAH and TAL are constrained to lie between

zero and TS.

PWM signals similar to those illustrated in Figure 7 and Figure 8 can

be produced on the BH, BL, CH, and CL outputs by programming

the PWMCHB and PWMCHC Registers in a manner identical

to that described for PWMCHA.

The PWM controller does not produce any PWM outputs until

all of the PWMTM, PWMCHA, PWMCHB, and PWMCHC

Registers have been written to at least once. After these registers

have been written, the counters in the three-phase timing unit

are enabled. Writing to these registers also starts the main PWM

timer. If during initialization, the PWMTM Register is written

before the PWMCHA, PWMCHB, and PWMCHC Registers, the

ﬁrst PWMSYNC pulse (and interrupt if enabled) will be generated

(1.5

× T

× PWMTM) seconds after the initial write to the

PWMTM Register in single update mode. In double update mode,

the ﬁrst PWMSYNC pulse will be generated (TCK

× PWMTM)

seconds after the initial write to the PWMTM Register in single

update mode.

Effective PWM Resolution

In single update mode, the same values of PWMCHA, PWMCHB,

and PWMCHC are used to deﬁne the on-times in both half

cycles of the PWM period. As a result, the effective resolution of

the PWM generation process is 2 TCK (or 100 ns for a 20 MHz

CLKOUT) since incrementing one of the duty cycle registers by

one changes the resultant on-time of the associated PWM signals

by TCK in each half period (or 2 TCK for the full period).

In double update mode, improved resolution is possible since

different values of the duty cycle registers are used to deﬁne the

on-times in both the ﬁrst and second halves of the PWM period.

As a result, it is possible to adjust the on-time over the whole

period in increments of TCK. This corresponds to an effective

PWM resolution of TCK in double update mode (or 50 ns for a

20 MHz CLKOUT).

Table IV. Fundamental Characteristics of PWM Generation Unit of ADMCF340

16-BIT PWM TIMER

Parameter

Min

Typ

Max

Unit

Counter Resolution

Bits

Edge Resolution (Single Update Mode)

100

Edge Resolution (Double Update Mode)

Programmable Dead Time Range

102

µs

Programmable Dead Time Increments

100

Programmable Pulse Deletion Range

µs

Programmable Pulse Deletion Increments

PWM Frequency Range

153

PWMSYNC Pulsewidth (TCRST)

0.05

12.8

µs

Gate Drive Chop Frequency Range

0.02

MHz

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