ADMCF340BST datasheet(22/40 Pages) AD

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ADMCF340

–22–

Analog Front End

The main analog inputs of the ADMCF340 (ISENSE1 through

ISENSE3) are connected to the ADC converter through three

front end blocks. Figure 14 shows the block diagram of a single

analog front end.

Each analog front end has two analog inputs: voltage and

current. A 2-to-1 multiplexer selects which input will be

converted; the multiplexer selection is determined by the

MODECTRL Register.

The current input (ISENSE) is amplified through a bipolar amplifier

(Gain –2.5). There is an output offset that matches the amplifier

output signal range to the input signal range of the A/D converter.

The amplifier has a built-in over current and open circuit protec-

tion. The over current protection shuts down the PWM block

when the voltage at any of the ISENSE pins exceeds the trip thresh-

old (high or low). The open-circuit protection shuts down the

PWM block when any of the ISENSE inputs is in high impedance

(for example the current sense resistor or the current transducer

is disconnected). The shut-down signals generated by the amplifi-

ers are then OR-ed and filtered in order to avoid spurious trip

caused by the switching of the power devices. The amplifier is

followed by a sample-and-hold amplifier (SHA). The SHA time

is user-programmable through the SHA Timer Register. The

sampling time is set as a delay from the rising edge of the

PWMSYNC signal and is calculated as:

SHA CNT

SAMPLE

() ×

The SHA Timer Counter has a minimum reload value of 0x0003,

which ensures a minimum settling time of the SHA output in

case the user is programming the SHA Timer Register to a value

smaller than 0x0003. This means that the sampling time is program-

mable from 5 TCK to 65535 TCK (corresponding to 250 ns to

3.28 ms for a CLKOUT rate of 20 MHz). The sampling time,

however, is limited to the rising edge of the following PWMSYNC

cycle. Each channel has an independent amplifier, SHA, and

SHA timing unit/state machine. Figure 15 shows a conversion

sequence of a single channel.

At the beginning of the cycle N (rising edge of PWMSYNC

signal (1)), the Timer Counter is loaded with the value con-

tained in the SHA_CNT Register. After the Timer Counter has

been reloaded, it starts counting down at the CLKOUT rate; in

this phase the SHA state-machine forces the SHA in TRACK

(sample) status.

When the counter reaches the value of 0x0000 (after the time

TSAMPLE from the rising edge of PWMSYNC), the SHA state-

machine forces the SHA in HOLD status.

The conversion of the sampled value is then taking place in the

cycle N + 1 (from (4) to (5)) in Figure 16 and the result of the

conversion is available on the ADC Register at the cycle N + 2

(rising edge of PWMSYNC (5)).

On cycle N + 2, the reload value of the Timer Counter exceeds the

period of the PWMSYNC signal. In this case the SHA state ma-

chine forces the SHA in HOLD status at the rising edge of

PWMSYNC of the next cycle (7). The conversion then takes place

on cycle N + 3 and the conversion result is available on the ADC

During the acquire phase (the PWMSYNC cycle during the

sampling of the input value) the conversion takes place. How-

ever, the value on the ADC Register is not considered valid.

This condition is signaled by the ADC by setting the LSB of the

ADC Register to high.

On cycle N + 4, at the rising edge of the PWMSYNC signal (9),

the Timer Counter is reloaded with a value smaller than the

PWMSYNC pulsewidth. In this case the SHA samples within

the PWMSYNC pulsewidth and the conversion takes place in

the same PWMSYNC cycle (from (10) to (11)).

N – 1

N + 1

N + 2

N + 3

N + 4

N + 5

CYCLE

PWMSYNC

SHA TIMER

COUNTER

SHA STATUS

ISENSE INPUT

ADC REGISTER

DATA READY

SAMPLED ON

CYCLE N – 2

INVALID

LSB = 1

DATA READY

SAMPLED ON

CYCLE N

INVALID

LSB = 1

DATA READY

SAMPLED ON

CYCLE N + 2

DATA READY

SAMPLED ON

CYCLE N + 4

TSAMPLE

TRACK

Figure 15. ADC Conversion Sequence of a Current Input

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