ADMCF340BST datasheet(15/40 Pages) AD

15 / 40 page

REV. 0

ADMCF340

–15–

which means that the width of the pulse is programmable from TCK

to 256 TCK (corresponding to 50 ns to 12.8

µs for a CLKOUT

rate of 20 MHz). Following a reset, the PWMSYNCWT Register

contains 0x27 (= 39) so that the default PWMSYNC width is 2.0

µs.

PWM Duty Cycles: PWMCHA, PWMCHB, PWMCHC

Registers

The duty cycles of the six PWM output signals are controlled by

the three duty cycle registers, PWMCHA, PWMCHB, and

PWMCHC. The integer value in the register PWMCHA controls

the duty cycle of the signals on AH and AL. PWMCHB controls

the duty cycle of the signals on BH and BL, and PWMCHC

controls the duty cycle of the signals on CH and CL. The duty cycle

registers are programmed in integer counts of the fundamental

time unit, TCK, and define the desired on-time of the high side

PWM signal produced by the three-phase timing unit over half the

PWM period. The switching signals produced by the three-phase

timing unit are also adjusted to incorporate the programmed dead

time value in the PWMDT Register.

The PWM is center-based. This means that in single update mode,

the resulting output waveforms are symmetrical and centered

in the PWMSYNC period. Figure 7 presents a typical PWM timing

diagram illustrating the PWM-related registers’ (PWMCHA,

PWMTM, PWMDT, and PWMSYNCWT) control over the

waveform timing in both half cycles of the PWM period. The

magnitude of each parameter in the timing diagram is determined by

multiplying the integer value in each register by TCK (typically

50 ns). It may be seen in the timing diagram how dead time is

incorporated into the waveforms by moving the switching edges

away from the original values set in the PWMCHA Register.

PWMCHA

PWMDT

PWMSYNCWT + 1

PWMCHA

PWMTM

PWMSYNC

SYSSTAT (3)

PWMDT

Figure 7. Typical PWM Outputs of Three-Phase Timing

Unit in Single Update Mode

Each switching edge is moved by an equal amount (PWMDT

× TCK) to preserve the symmetrical output patterns. The

PWMSYNC pulse, whose width is set by the PWMSYNCWT

which half cycle is active. This can be useful in double update

mode, to be discussed later in this data sheet.

The resultant on-times of the PWM signals shown in Figure 5

may be written as:

TPWMCHA

PWMDT

TPWMTM

PWMCHA

PWMDT

=×

(–

)

(–

–

)

The corresponding duty cycles are:

PWMCHA

PWMDT

PWMTM

PWMCHA

PWMDT

PWMTM

–

––

Obviously, negative values of TAH and TAL are not permitted

because the minimum permissible value is zero, corresponding

to a 0% duty cycle. In a similar fashion, the maximum value is

TS, corresponding to a 100% duty cycle.

The output signals from the timing unit for operation in double

update mode are shown in Figure 8. This illustrates a completely

general case where the switching frequency, dead time, and duty

cycle are all changed in the second half of the PWM period. Of

course, the same value for any or all of these quantities could be

used in both halves of the PWM cycle. However, it can be seen

that there is no guarantee that symmetrical PWM signals will be

produced by the timing unit in this double update mode.

Additionally, it is seen that the dead time is inserted into the PWM

signals in the same way as in the single update mode.

PWMCHA2

PWMDT1

PWMDT2

PWMSYNCWT2 + 1

PWMCHA1

PWMTM1

PWMTM2

PWMSYNCWT1 + 1

PWMSYNC

SYSSTAT (3)

Figure 8. Typical PWM Outputs of Three-Phase Timing

Unit in Double Update Mode

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