AD9772AST datasheet(18/30 Pages) AD

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AD9772

–18–

complementary output with the full-scale current split between

the two outputs as a function of the input code.

The digital interface is implemented using an edge-triggered

master slave latch and is designed to support an input data rate

as high as 150 MSPS. The clock can be operated at any duty

cycle that meets the specified latch pulsewidth as shown in Figures

1a and 1b. The setup and hold times can also be varied within

the clock cycle as long as the specified minimum times are

met. The digital inputs (excluding CLK+ and CLK–) are CMOS-

compatible with its logic thresholds, VTHRESHOLD, set to approxi-

mately half the digital positive supply (i.e., DVDD or CLKVDD)

VTHRESHOLD = DVDD/2 (

±20%)

The internal digital circuitry of the AD9772 is capable of operating

over a digital supply range of 2.7 V to 3.6 V. As a result, the

digital inputs can also accommodate TTL levels when DVDD is

set to accommodate the maximum high level voltage of the TTL

drivers VOH(MAX). Although a DVDD of 3.3 V will typically

ensure proper compatibility with most TTL logic families, a

series 200

Ω resistors are recommended between the TTL logic

driver and digital inputs to limit the peak current through the

ESD protection diodes if VOH(MAX) exceeds DVDD by more

than 300 mV. Figure 36 shows the equivalent digital input cir-

cuit for the data and control inputs.

DIGITAL

INPUT

DVDD

Figure 36. Equivalent Digital Input

The AD9772 features a flexible differential clock input operat-

ing from separate supplies (i.e., CLKVDD, CLKCOM) to

achieve optimum jitter performance. The two clock inputs,

CLK+ and CLK–, can be driven from a single-ended or

differential clock source. For single-ended operation, CLK+

should be driven by a single-ended logic source while CLK–

should be set to the logic source’s threshold voltage via a resistor

divider/capacitor network referenced to CLKVDD as shown in

Figure 37. For differential operation, both CLK+ and CLK–

should be biased to CLKVDD/2 via a resistor divider network

as shown in Figure 38. An RF transformer as shown in Figure 3

can also be used to convert a single-ended clock input to a dif-

ferential clock input.

RSERIES

VTHRESHHOLD

AD9772

CLK+

CLKVDD

CLK–

CLKCOM

0.1 F

Figure 37. Single-Ended Clock Interface

AD9772

CLK+

CLKVDD

CLK–

CLKCOM

0.1 F

ECL/PECL

Figure 38. Differential Clock Interface

The quality of the clock and data input signals are important in

achieving the optimum performance. The external clock driver

circuitry should provide the AD9772 with a low jitter clock

input meeting the min/max logic levels while providing fast

edges. Although fast clock edges help minimize any jitter that

will manifest itself as phase noise on a reconstructed waveform,

the high gain-bandwidth product of the AD9772’s differential

comparator can tolerate sine wave inputs as low as 0.5 V p-p,

with minimal degradation in its output noise floor.

Digital signal paths should be kept short and run lengths matched

to avoid propagation delay mismatch. The insertion of a low

value resistor network (i.e., 50

Ω to 200 Ω) between the AD9772

digital inputs and driver outputs may be helpful in reducing any

overshooting and ringing at the digital inputs that contribute to

data feedthrough.

SLEEP MODE OPERATION

The AD9772 has a SLEEP function that turns off the output

current and reduces the analog supply current to less than

6 mA over the specified supply range of 2.7 V to 3.6 V. This

mode can be activated by applying a Logic Level “1” to the

SLEEP pin. The AD9772 takes less than 50 ns to power down

and approximately 15

µs to power back up.

POWER DISSIPATION

The power dissipation, PD, of the AD9772 is dependent on

several factors, including:

1. AVDD, PLLVDD, CLKVDD and DVDD, the power supply

voltages

2. IOUTFS, the full-scale current output

3. fDATA, the update rate

4. the reconstructed digital input waveform.

The power dissipation is directly proportional to the analog

supply current, IAVDD, and the digital supply current, IDVDD.

IAVDD is directly proportional to IOUTFS, and is insensitive to

fDATA.

Conversely, IDVDD is dependent on both the digital input wave-

form and fDATA. Figure 39 shows IDVDD as a function of full-

scale sine wave output ratios (fOUT/fDATA) for various update

rates with DVDD = 3 V. The supply current from CLKVDD

and PLLVDD is relatively insensitive to the digital input wave-

form, but shown directly proportional to the update rate as

shown in Figure 40.

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