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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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AD9772AST датащи(PDF) 4 Page - Analog Devices |
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AD9772AST датащи(HTML) 4 Page - Analog Devices |
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4 / 30 page  REV. 0 –4– AD9772–SPECIFICATIONS DIGITAL SPECIFICATIONS (TMIN to TMAX, AVDD = +3 V, CLKVDD = +3 V, PLLVDD = +0 V, DVDD = +3 V, IOUTFS = 20 mA, unless otherwise noted) Parameter Min Typ Max Units DIGITAL INPUTS Logic “1” Voltage 2.1 3 V Logic “0” Voltage 0 0.9 V Logic “1” Current 1 –10 +10 µA Logic “0” Current –10 +10 µA Input Capacitance 5 pF CLOCK INPUTS Input Voltage Range 0 3 V Common-Mode Voltage 0.75 1.5 2.25 V Differential Voltage 0.5 1.5 V PLL CLOCK ENABLED—FIGURE 1a Input Setup Time (tS) 1.0 ns Input Hold Time (tH) 2.5 ns Latch Pulsewidth (tLPW) 1.5 ns PLL CLOCK DISABLED—FIGURE 1b Input Setup Time (tS) 1.0 ns Input Hold Time (tH) 2.5 ns Latch Pulsewidth (tLPW) 1.5 ns CLK/PLLLOCK Delay (tOD) 5 ns NOTES 1MOD1 and MOD0 have typical input currents of 120 µA while SLEEP has a typical input current of 15 µA. Specifications subject to change without notice. tS 0.025% 0.025% DB0–DB13 CLK+ – CLK– IOUTA OR IOUTB tH tLPW tPD tST Figure 1a. Timing Diagram—PLL Clock Multiplier Enabled tS DB0–DB13 0.025% 0.025% IOUTA OR IOUTB tOD PLLLOCK CLK+ – CLK– tH tLPW tPD tST Figure 1b. Timing Diagram—PLL Clock Multiplier Disabled |
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