AD9772AST datasheet(14/30 Pages) AD

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AD9772

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The PLL clock multiplier has two modes of operation. It can be

enabled for less demanding applications providing a reference

clock meeting the minimum specified input data rate of 6 MSPS.

It can be disabled for applications below this data rate or for

applications requiring higher phase noise performance. In this

case, a reference clock at twice the input data rate (i.e., 2

× f

DATA)

must be provided without the “zero stuffing” option selected and

four times the input data rate (i.e., 4

× f

DATA) with the “zero

stuffing” option selected. Note, multiple AD9772 devices can

be synchronized in either mode if driven by the same reference

clock since the PLL clock multiplier when enabled ensures

synchronization. RESET can be used for synchronization if the

PLL clock multiplier is disabled.

Figure 26 shows the proper configuration used to enable the

PLL clock multiplier. In this case, the external clock source is

applied to CLK+ (and/or CLK–) and the PLL clock multiplier is

fully enabled by connecting PLLVDD to CLKVDD. An external

PLL loop filter consisting of a series resistor and ceramic capaci-

tor connected from the output of the charge pump (i.e., LPF) to

PLLVDD is required for stability of the PLL. Also, a shield

surrounding these components is recommended to minimize

external noise coupling into the VCO input.

The components values shown (i.e., 392

Ω and 1.0 µF) were

selected to optimize the phase noise vs. settling/acquisition time

characteristics of the PLL. The settling/acquisition time character-

istics are also dependent on the divide-by-N ratio as well as the

input data rate. In general, the acquisition time increases with

increasing data rate (for fixed divide-by-N ratio) or increasing

divide-by-N ratio (for fixed input data rate).

Since the VCO can operate over a 96 MHz–400 MHz range,

the prescaler divide-by-ratio following the VCO must be set

according to Table III for a given input data rate (i.e., fDATA)

to ensure optimum phase noise and successful “locking.” In

general, the best phase noise performance for any prescaler

setting is achieved with the VCO operating near its maximum

output frequency of 400 MHz. Note, the divide-by-N ratio

also depends on whether the “zero stuffing” option is enabled

since this option requires the DAC to operate at four times

the input data rate. The divide-by-N ratio is set by DIV1 and

DIV0.

Table III. Recommended Prescaler Divide-by-N Ratio Settings

fDATA

Divide-by-N

(MSPS)

MOD1

DIV1

DIV0

Ratio

48–150

24–100

12–50

6–25

24–100

12–50

6–25

3–12.5

With the PLL clock multiplier enabled, PLLLOCK serves as an

active HIGH control output which may be monitored upon sys-

tem power-up to indicate that the PLL is successfully “locked” to

the input clock. Note, when the PLL clock multiplier is NOT

locked, PLLLOCK will toggle between logic HIGH and LOW

in an asynchronous manner until locking is finally achieved.

As a result, it is recommended that PLLLOCK, if monitored,

be sampled several times to detect proper locking 100 ms

upon power-up.

As stated earlier, applications requiring input data rates below

6 MSPS must disable the PLL clock multiplier and provide an

external reference clock. However, applications already contain-

ing a low phase noise (i.e., jitter) reference clock that is twice

(or four times) the input data rate should consider disabling the

PLL clock multiplier to achieve the best SNR performance from

the AD9772. Note, the SFDR performance and wideband noise

performance of the AD9772 remains unaffected with or without

the PLL clock multiplier enabled.

The effects of phase noise on the AD9772’s SNR performance

becomes more noticeable at higher reconstructed output fre-

quencies and signal levels. Figure 27 compares the phase noise

of a full-scale sine wave at exactly fDATA/4 at different data rates

(hence carrier frequency) with the optimum DIV1, DIV0 set-

ting. The effects of phase noise, and its effect on a signal’s CNR

performance, becomes even more evident at higher IF fre-

quencies as shown in Figure 28. In both instances, it is the

“narrowband” phase noise that limits the CNR performance.

FREQUENCY OFFSET – MHz

–20

–100

1234

–40

–60

–80

50 MSPS WITH DIV4

100 MSPS WITH DIV2

75 MSPS WITH DIV2

WITHOUT PLL

150 MSPS WITH DIV1

Figure 27. Phase Noise of PLL Clock Multiplier @ Exactly

fOUT = fDATA/4 at Different fDATA Settings with Optimum

DIV0/DIV1 Settings Using R & S FSEA30 Spectrum

Analyzer

FREQUENCY – MHz

–20

–100

100

150

110

120

130

140

–40

–60

–80

PLL WITH DIV = 8

WITHOUT PLL

Figure 28. Direct IF Mode Reveals Phase Noise Degrada-

tion With and Without PLL Clock Multiplier (IF = 125 MHz

and fDATA = 100 MSPS)

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