поискавой системы для электроныых деталей
  Russian  ▼
ALLDATASHEETRU.COM

X  

AD9772AST датащи(PDF) 11 Page - Analog Devices

номер детали AD9772AST
подробное описание детали  14-Bit, 150 MSPS TxDAC??with 2x Interpolation Filter
PDF  30 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
производитель  AD [Analog Devices]
домашняя страница  http://www.analog.com
Logo AD - Analog Devices

AD9772AST датащи(HTML) 11 Page - Analog Devices

Back Button AD9772AST Datasheet HTML 7Page - Analog Devices AD9772AST Datasheet HTML 8Page - Analog Devices AD9772AST Datasheet HTML 9Page - Analog Devices AD9772AST Datasheet HTML 10Page - Analog Devices AD9772AST Datasheet HTML 11Page - Analog Devices AD9772AST Datasheet HTML 12Page - Analog Devices AD9772AST Datasheet HTML 13Page - Analog Devices AD9772AST Datasheet HTML 14Page - Analog Devices AD9772AST Datasheet HTML 15Page - Analog Devices Next Button
Zoom Inzoom in Zoom Outzoom out
 11 / 30 page
background image
REV. 0
AD9772
–11–
FUNCTIONAL DESCRIPTION
Figure 22 shows a simplified block diagram of the AD9772.
The AD9772 is a complete, 2
× oversampling, 14-bit DAC that
includes a 2
× interpolation filter, a phase-locked loop (PLL)
clock multiplier and a 1.20 V bandgap voltage reference. While
the AD9772’s digital interface can support input data rates as
high as 150 MSPS, its internal DAC can operate up to 400 MSPS,
thus providing direct IF conversion capabilities. The 14-bit
DAC provides two complementary current outputs whose full-
scale current is determined by an external resistor. The AD9772
features a flexible, low jitter, differential clock input providing
excellent noise rejection while accepting a sine wave input. An
on-chip PLL clock multiplier produces all of the necessary
synchronized clocks from an external reference clock source.
Separate supply inputs are provided for each functional block to
ensure optimum noise and distortion performance. A SLEEP
mode is also included for power savings.
14-BIT DAC
ZERO
STUFF
MUX
2
FIR
INTERPOLATION
FILTER
EDGE-
TRIGGERED
LATCHES
CLOCK DISTRIBUTION
AND MODE SELECT
2 /4
MUX
CONTROL
FILTER
CONTROL
1 /2
1
PLL CLOCK
MULTIPLIER
+1.2V REFERENCE
AND CONTROL AMP
AD9772
CLKCOM CLKVDD
MOD0 MOD1
RESET
PLLLOCK
DIV0 DIV1
CLK+
CLK–
DATA
INPUTS
(DB13...DB0)
SLEEP
DCOM
DVDD
ACOM
AVDD
REFLO
PLLCOM
LPF
PLLVDD
IOUTA
IOUTB
REFIO
FSADJ
Figure 22. Functional Block Diagram
Preceding the 14-bit DAC is a 2
× digital interpolation filter that
can be configured for a low pass (i.e., baseband mode) or high
pass (i.e., direct IF mode) response. The input data is latched
into the edge-triggered input latches on the rising edge of the
differential input clock as shown in Figure 1a and then interpo-
lated by a factor of two by the digital filter. For traditional base-
band applications, the 2
× interpolation filter has a low pass
response. For direct IF applications, the filter’s response can be
converted into a high pass response to extract the higher image.
The output data of the 2
× interpolation filter can update the
14-bit DAC directly or undergo a “zero-stuffing” process to
increase the DAC update rate by another factor of two. This
action enhances the relative signal level and passband flatness of
the higher images.
DIGITAL MODES OF OPERATION
The AD9772 features four different digital modes of operation
controlled by the digital inputs, MOD0 and MOD1. MOD0
controls the 2
× digital filter’s response (i.e., low pass or high
pass), while MOD1 controls the “zero-stuffing” option. The
selected mode as shown in Table II will depend on whether the
application requires the reconstruction of a baseband or IF signal.
Table II. Digital Modes
Digital
Digital
Zero-
Mode
MOD0
MOD1
Filter
Stuffing
Baseband
0
0
Low
No
Baseband
0
1
Low
Yes
Direct IF
1
0
High
No
Direct IF
1
1
High
Yes
Applications requiring the highest dynamic range over a wide
bandwidth should consider operating the AD9772 in a baseband
mode. Note, the “zero-stuffing” option can also be used in this
mode although the ratio of signal to image power will be re-
duced. Applications requiring the synthesis of IF signals should
consider operating the AD9772 in a Direct IF mode. In this
case, the “zero-stuffing” option should be considered when
synthesizing and selecting IFs beyond the input data rate, fDATA.
If the reconstructed IF falls below fDATA, the “zero-stuffing”
option may or may not be beneficial. Note, the dynamic range
(i.e., SNR/SFDR) is also optimized by disabling the PLL Clock
Multiplier (i.e., PLLVDD to PLLCOM) and using an external
low jitter clock source operating at the DAC update rate, fDAC.
2
Interpolation Filter Description
The 2
× interpolation filter is based on a 43-tap half-band sym-
metric FIR topology that can be configured for a low or high
pass response, depending on state of the MOD0 control input.
The low pass response is selected with MOD0 LOW while the
high pass response is selected with MOD0 HIGH. The low pass
frequency and impulse response of the half-band interpolation
filter are shown in Figures 2a and 2b, while Table I lists the
idealized filter coefficients. Note, a FIR filter’s impulse response
is also represented by its idealized filter coefficients.
The 2
× interpolation filter essentially multiplies the input data
rate to the DAC by a factor of two, relative to its original input
data rate, while simultaneously reducing the magnitude of the
1st image associated with the original input data rate occurring
at fDATA – fFUNDAMENTAL. Note, as a result of the 2
× interpola-
tion, the digital filter’s frequency response is uniquely defined
over its Nyquist zone of dc to fDATA, with mirror images occur-
ring in adjacent Nyquist zones.
The benefits of an interpolation filter are clearly seen in Figure
23, which shows an example of the frequency and time domain
representation of a discrete time sine wave signal before and
after it is applied to the 2
× digital interpolation filter in a low
pass configuration. Images of the sine wave signal appear around
multiples of the DAC’s input data rate (i.e., fDATA) as predicted
by sampling theory. These undesirable images will also appear
at the output of a reconstruction DAC, although attenuated by
the DAC’s sin(x)/x roll-off response.
In many bandlimited applications, the images from the recon-
struction process must be suppressed by an analog filter follow-
ing the DAC. The complexity of this analog filter is typically
determined by the proximity of the desired fundamental to the
first image and the required amount of image suppression. Add-
ing to the complexity of this analog filter may be the require-
ment of compensating for the DAC’s sin(x)/x response.



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30


датащи скачать

Go To PDF Page


ссылки URL



Вашему бизинису помогли Аллдатащит?  [ DONATE ] 

Что такое Аллдатащит   |   реклама   |   контакт   |   Конфиденциальность   |   Ссылка на техническое описание    |   обмен ссыками   |   поиск по производителю
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com