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AD7705 датащи(PDF) 25 Page - Analog Devices |
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AD7705 датащи(HTML) 25 Page - Analog Devices |
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25 / 32 page ![]() AD7705/AD7706 –25– REV. A POWER-ON/RESET FOR AD7705 CONFIGURE & INITIALIZE C/ P SERIAL PORT WRITE TO COMMUNICATIONS REGISTER SELECTING CHANNEL & SETTING UP NEXT OPERATION TO BE A WRITE TO THE CLOCK REGISTER (20 HEX) WRITE TO CLOCK REGISTER SETTING THE CLOCK BITS IN ACCORDANCE WITH THE APPLIED MASTER CLOCK SIGNAL AND SELECT UPDATE RATE FOR SELECTED CHANNEL (0C HEX) WRITE TO COMMUNICATIONS REGISTER SELECTING CHANNEL & SETTING UP NEXT OPERATION TO BE A WRITE TO THE SETUP REGISTER (10 HEX) WRITE TO SETUP REGISTER CLEARING F SYNC, SETTING UP GAIN, OPERATING CONDITIONS & INITIATING A SELF-CALIBRATION ON SELECTED CHANNEL (40 HEX) POLL DRDY PIN NO YES WRITE TO COMMUNICATIONS REGISTER SETTING UP NEXT OPERATION TO BE A READ FROM THE DATA REGISTER (38 HEX) READ FROM DATA REGISTER WRITE TO COMMUNICATIONS REGISTER SETTING UP NEXT OPERATION TO BE A READ FROM THE COMMUNICATIONS REGISTER (08 HEX) READ FROM COMMUNICATIONS REGISTER POLL DRDY BIT OF COMMUNICATIONS REGISTER WRITE TO COMMUNICATIONS REGISTER SETTING UP NEXT OPERATION TO BE A READ FROM THE DATA REGISTER (38 HEX) START READ FROM DATA REGISTER DRDY LOW? NO YES DRDY LOW? Figure 18. Flowchart for Setting Up and Reading from the AD7705 CONFIGURING THE AD7705/AD7706 The AD7705/AD7706 contains six on-chip registers that the user can accesses via the serial interface. Communication with any of these registers is initiated by writing to the Communica- tions Register first. Figure 18 outlines a flow diagram of the sequence used to configure all registers after a power-up or reset on the AD7705, similar procedures apply to the AD7706. The flowchart also shows two different read options—the first where the DRDY pin is polled to determine when an update of the data register has taken place, the second where the DRDY bit of the Communications Register is interrogated to see if a data register update has taken place. Also included in the flowing dia- gram is a series of words that should be written to the registers for a particular set of operating conditions. These conditions are gain of one, no filter sync, bipolar mode, buffer off, clock of 4.9512 MHz and an output rate of 50 Hz. |
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