AD7705 datasheet(22/32 Pages) AD

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AD7705/AD7706

–22–

REV. A

Placing the part in standby mode reduces the total current to

µA typical with V

DD = 5 V and 4

µA with V

DD = 3 V when the

part is operated from an external master clock provided this

master clock is stopped. If the external clock continues to run in

standby mode, the standby current increases to 150

µA typical

with 5 V supplies and 75

µA typical with 3.3 V supplies. If a

crystal or ceramic resonator is used as the clock source, the total

current in standby mode is 400

µA typical with 5 V supplies and

µA with 3.3 V supplies. This is because the on-chip oscillator

circuit continues to run when the part is in its standby mode.

This is important in applications where the system clock is pro-

vided by the AD7705/AD7706’s clock, so that the AD7705/

AD7706 produces an uninterrupted master clock even when it is

in its standby mode.

Accuracy

Sigma-Delta ADCs, like VFCs and other integrating ADCs, do

not contain any source of nonmonotonicity and inherently offer

no missing codes performance. The AD7705/AD7706 achieves

excellent linearity by the use of high quality, on-chip capacitors,

which have a very low capacitance/voltage coefficient. The de-

vice also achieves low input drift through the use of chopper-

stabilized techniques in its input stage. To ensure excellent

performance over time and temperature, the AD7705/AD7706

uses digital calibration techniques that minimize offset and gain

error.

Drift Considerations

The AD7705/AD7706 uses chopper stabilization techniques to

minimize input offset drift. Charge injection in the analog

switches and dc leakage currents at the sampling node are the

primary sources of offset voltage drift in the converter. The dc

input leakage current is essentially independent of the selected

gain. Gain drift within the converter depends primarily upon

the temperature tracking of the internal capacitors. It is not

affected by leakage currents.

Measurement errors due to offset drift or gain drift can be

eliminated at any time by recalibrating the converter. Using

the system calibration mode can also minimize offset and gain

errors in the signal conditioning circuitry. Integral and differen-

tial linearity errors are not significantly affected by temperature

changes.

POWER SUPPLIES

The AD7705/AD7706 operates with a VDD power supply be-

tween 2.7 V and 5.25 V. While the latch-up performance of the

AD7705/AD7706 is good, it is important that power is applied

to the AD7705/AD7706 before signals at REF IN, AIN or the

logic input pins in order to avoid excessive currents. If this is not

possible, the current that flows in any of these pins should be

limited. If separate supplies are used for the AD7705/AD7706

and the system digital circuitry, the AD7705/AD7706 should be

powered up first. If it is not possible to guarantee this, current

limiting resistors should be placed in series with the logic

inputs to again limit the current. Latch-up current is greater

than 100 mA.

Supply Current

The current consumption on the AD7705/AD7706 is specified

for supplies in the range +2.7 V to +3.3 V and in the range +4.75 V

to +5.25 V. The part operates over a +2.7 V to +5.25 V supply

range and the IDD for the part varies as the supply voltage varies

over this range. There is an internal current boost bit on the

AD7705/AD7706 that is set internally in accordance with the

operating conditions. This affects the current drawn by the

analog circuitry within these devices. Minimum power consump-

tion is achieved when the AD7705/AD7706 is operated with an

fCLKIN of 1 MHz or at gains of 1 to 4 with fCLKIN = 2.4575 MHz

as the internal boost bit is off reducing the analog current con-

sumption. Figure 15 shows the variation of the typical IDD with

VDD voltage for both a 1 MHz crystal oscillator and a 2.4576 MHz

crystal oscillator at +25

°C. The AD7705/AD7706 is operated in

unbuffered mode. The relationship shows that the IDD is mini-

mized by operating the part with lower VDD voltages. IDD on the

AD7705/AD7706 is also minimized by using an external master

clock or by optimizing external components when using the

on-chip oscillator circuit. Figures 3, 4, 6 and 7 show variations

in IDD with gain, VDD and clock frequency using an external

clock.

VDD

1600

1400

800

600

400

200

1200

1000

2.5

5.5

3.0

3.5

4.0

4.5

5.0

MCLK IN = CRYSTAL OSCILLATOR

TA = +25 C

UNBUFFERED MODE

GAIN = 128

fCLK = 2.4576MHz

fCLK = 1MHz

Figure 15. IDD vs. Supply Voltage

Grounding and Layout

Since the analog inputs and reference input are differential, most

of the voltages in the analog modulator are common-mode volt-

ages. The excellent common-mode rejection of the part will

remove common-mode noise on these inputs. The digital filter

will provide rejection of broadband noise on the power supplies,

except at integer multiples of the modulator sampling frequency.

The digital filter also removes noise from the analog and refer-

ence inputs provided those noise sources do not saturate the

analog modulator. As a result, the AD7705/AD7706 is more

immune to noise interference than a conventional high resolu-

tion converter. However, because the resolution of the AD7705/

AD7706 is so high, and the noise levels from the AD7705/

AD7706 so low, care must be taken with regard to grounding

and layout.

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