AD7705 datasheet(24/32 Pages) AD

24 / 32 page

AD7705/AD7706

–24–

REV. A

Figures 16 and 17 show timing diagrams for interfacing to the

AD7705/AD7706 with

CS used to decode the part. Figure 16 is

for a read operation from the AD7705/AD7706’s output shift

shift register. It is possible to read the same data twice from the

output register even though the

DRDY line returns high after

the first read operation. Care must be taken, however, to ensure

that the read operations have been completed before the next

output update is about to take place.

The AD7705/AD7706 serial interface can operate in three-wire

mode by tying the

CS input low. In this case, the SCLK, DIN

and DOUT lines are used to communicate with the AD7705/

AD7706 and the status of

DRDY can be obtained by interrogat-

ing the MSB of the Communications Register. This scheme is

suitable for interfacing to microcontrollers. If

CS is required as a

decoding signal, it can be generated from a port bit. For

microcontroller interfaces, it is recommended that the SCLK

idles high between data transfers.

The AD7705/AD7706 can also be operated with

CS used as a

frame synchronization signal. This scheme is suitable for DSP

interfaces. In this case, the first bit (MSB) is effectively clocked

out by

CS since CS would normally occur after the falling edge

of SCLK in DSPs. The SCLK can continue to run between

data transfers provided the timing numbers are obeyed.

DRDY

t10

SCLK

DOUT

MSB

LSB

Figure 16. Read Cycle Timing Diagram

t11

t14

t15

t12

t16

SCLK

DIN

MSB

LSB

t13

Figure 17. Write Cycle Timing Diagram

The serial interface can be reset by exercising the

RESET input

on the part. It can also be reset by writing a series of 1s on the

DIN input. If a Logic 1 is written to the AD7705/AD7706 DIN

line for at least 32 serial clock cycles the serial interface is reset.

This ensures that in three-wire systems, if the interface gets lost

either via a software error or by some glitch in the system, it can

be reset back to a known state. This state returns the interface

to where the AD7705/AD7706 is expecting a write operation to

its Communications Register. This operation in itself does not

reset the contents of any registers but since the interface was

lost, the information written to any of the registers is unknown

and it is advisable to set up all registers again.

Some microprocessor or microcontroller serial interfaces have a

single serial data line. In this case, it is possible to connect the

AD7705/AD7706’s DATA OUT and DATA IN lines together

and connect them to the single data line of the processor. A

10 k

Ω pull-up resistor should be used on this single data line. In

this case, if the interface gets lost, because the read and write

operations share the same line the procedure to reset it back to a

known state is somewhat different than previously described. It

requires a read operation of 24 serial clocks followed by a write

operation where a Logic 1 is written for at least 32 serial clock

cycles to ensure that the serial interface is back into a known

state.

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