AD7705/AD7706

–12–

REV. A

Setup Register (RS2, RS1, RS0 = 0, 0, 1); Power-On/Reset Status: 01 Hex

The Setup Register is an eight bit register from which data can either be read or to which data can be written. Table IX outlines the

bit designations for the Setup Register.

Table IX. Setup Register

MD1 (0)

MD0 (0)

G2 (0)

G1 (0)

G0 (0)

B/U (0)

BUF (0)

FSYNC (1)

MD1

MD0

Operating Mode

0

0

Normal Mode: this is the normal mode of operation of the device whereby the device is performing normal

conversions.

0

1

Self-Calibration: this activates self-calibration on the channel selected by CH1 and CH0 of the Communica-

tions Register. This is a one-step calibration sequence and when complete the part returns to Normal Mode

with MD1 and MD0 returning to 0, 0. The

DRDY output or bit goes high when calibration is initiated and

returns low when this self-calibration is complete and a new valid word is available in the data register. The

zero-scale calibration is performed at the selected gain on internally shorted (zeroed) inputs and the full-

1

0

Zero-Scale System Calibration: this activates zero scale system calibration on the channel selected by CH1

and CH0 of the Communications Register. Calibration is performed at the selected gain on the input volt-

age provided at the analog input during this calibration sequence. This input voltage should remain stable

for the duration of the calibration. The

DRDY output or bit goes high when calibration is initiated and

returns low when this zero-scale calibration is complete and a new valid word is available in the data register.

At the end of the calibration, the part returns to Normal Mode with MD1 and MD0 returning to 0, 0.

1

1

Full-Scale System Calibration: this activates full-scale system calibration on the selected input channel.

Calibration is performed at the selected gain on the input voltage provided at the analog input during this

calibration sequence. This input voltage should remain stable for the duration of the calibration. Once

again, the

DRDY output or bit goes high when calibration is initiated and returns low when this full-scale

calibration is complete and a new valid word is available in the data register. At the end of the calibration,

the part returns to Normal Mode with MD1 and MD0 returning to 0, 0.

G2–G0

Gain Selection Bits. These bits select the gain setting for the on-chip PGA as outlined in Table X.

Table X. Gain Selection

G2

G1

G0

Gain Setting

000

1

001

2

010

4

011

8

100

16

101

32

110

64

111

128

B/U

Bipolar/Unipolar Operation. A “0” in this bit selects Bipolar Operation. A “1” in this bit selects Unipolar Operation.

BUF

Buffer Control. With this bit at “0,” the on-chip buffer on the analog input is shorted out. With the buffer shorted

analog input allowing the input to handle higher source impedances.

FSYNC

Filter Synchronization. When this bit is high, the nodes of the digital filter, the filter control logic and the calibra-

tion control logic are held in a reset state and the analog modulator is also held in its reset state. When this bit

goes low, the modulator and filter start to process data and a valid word is available in 3

× 1/(output update rate),

i.e., the settling time of the filter. This FSYNC bit does not affect the digital interface and does not reset the

DRDY output if it is low.