REV. 0

AD5301/AD5311/AD5321

–14–

AD5301

A1

A0

SDA

SCL

AD5301

A1

A0

SDA

SCL

AD5301

A1

A0

SDA

SCL

AD5301

A1

A0

SDA

SCL

SCL

SDA

+5V

MASTER

Figure 33. Multiple AD5301 Devices on One Bus

The output voltage for any input code can be calculated as

follows:

× (R1 + R2)/R1) – V

where D is the decimal equivalent of the code loaded to the

DAC.

N is the DAC resolution.

Ω:

MULTIPLE DEVICES ON ONE BUS

Figure 33 shows four AD5301 devices on the same serial bus.

Each has a different slave address since the state of their A0 and

A1 pins is different. This allows each DAC to be written to or

read from independently. The master device output bus line

drivers are open-drain pull downs in a fully I

interface.

CMOS DRIVEN SCL AND SDA LINES

For single or multisupply systems where the minimum SCL

swing requirements allow it, a CMOS SCL driver may be used,

the SCL pull-up resistor can be removed, making the SCL bus

line fully CMOS compatible. This will reduce power consump-

tion in both the SCL driver and receiver devices. The SDA line

remains open-drain, I

Further changes, in the SDA line driver, may be made to make

the system more CMOS-compatible and save more power. As

the SDA line is bidirectional, it cannot be made fully CMOS-

compatible. A switched pull-up resistor can be combined with

a CMOS device with an open-circuit (three-state) input such

that the CMOS SDA driver is enabled during write cycles and

I

knowledge bit cycles, start and stop conditions.

POWER SUPPLY DECOUPLING

In any circuit where accuracy is important, careful consider-

ation of the power supply and ground return layout helps to

ensure the rated performance. The AD5301/AD5311/AD5321

should be decoupled to GND with a 10

µF in parallel with 0.1 µF

capacitor, located as close to the package as possible. The 10

µF

capacitor should be the tantalum bead type, while a ceramic

0.1

µF capacitor will provide sufficient low impedance path to

ground at high frequencies. The power supply lines of the

AD5301/AD5311/AD5321 should use as large a trace as pos-

sible to provide low impedance paths. A ground line routed

between the SDA and SCL lines will help reduce crosstalk

between them (not required on a multilayer board as there will

be a ground plane layer, but separating the lines will help).