REV. 0

AD5301/AD5311/AD5321

–5–

PIN CONFIGURATIONS

6-Lead SOT-23

8-Lead

SOIC

(RT-6)

(RM-8)

TOP VIEW

(Not to Scale)

6

5

4

1

2

3

GND

SDA

SCL

A0

TOP VIEW

(Not to Scale)

8

7

6

5

1

2

3

4

A0

PD

GND

SCL

SDA

A1

AD5301/AD5311/AD5321

AD5301/AD5311/AD5321

PIN FUNCTION DESCRIPTION

SOIC

SOT-23

Pin No.

Pin No.

Mnemonic

Function

16

Power Supply Input. These parts can be operated from +2.5 V to +5.5 V and the supply

should be decoupled with a 10

µF in parallel with a 0.1 µF capacitor to GND.

2

5

A0

Address Input. Sets the Least Significant Bit of the 7-bit slave address.

3

N/A

A1

Address Input. Sets the 2nd Least Significant Bit of the 7-bit slave address.

44

Buffered analog output voltage from the DAC. The output amplifier has rail-to-rail operation.

5

N/A

PD

Active low control input that acts as a hardware power-down option. This pin overrides any

software power-down option. The DAC output goes three-state and the current consumption

of the part drops to 50 nA @ 3 V (200 nA @ 5 V).

6

3

SCL

Serial Clock Line. This is used in conjunction with the SDA line to clock data into the 16-bit

ible interface. SCL may be CMOS/TTL driven.

7

2

SDA

Serial Data Line. This is used in conjunction with the SCL line to clock data into the 16-bit

input shift register during the write cycle and used to read back one or two bytes of data

(one byte for the AD5301, two bytes for the AD5311/AD5321) during the read cycle. It is

a bidirectional open-drain data line that should be pulled to the supply with an external

pull-up resistor. If not used in readback mode, SDA may be CMOS/TTL driven.

8

1

GND

Ground reference point for all circuitry on the part.