REV. 0

AD5301/AD5311/AD5321

–12–

READ OPERATION

When reading data back from the AD5301/AD5311/AD5321

DACs, the user must begin with an address byte after which the

DAC will acknowledge that it is prepared to transmit data by

pulling SDA low. There are two different read operations. In the

case of the AD5301, the readback is a single byte that consists

SCL

SDA

0

0

0

1

1

A1*

A0

R/

W

*THIS BIT MUST BE 0 IN THE 6-PIN SOT-23 VERSION.

ACK

BY

AD5301

START

COND

BY

MASTER

ADDRESS BYTE

D7

D6

D5

D4

D3

D2

D1

D0

NO ACK

BY

MASTER

STOP

COND

BY

MASTER

DATA BYTE

Figure 27. AD5301 Readback Sequence

SCL

SDA

SCL

SDA

D5

D4

D3

D2

D1

D0

X

X

X

X

PD1

PD0

D9

D8

D7

D6

0

0

0

1

1

A1*

A0

R/

W

NO ACK

BY

MASTER

STOP

COND

BY

MASTER

LEAST SIGNIFICANT BYTE

ACK

BY

AD5311

START

COND

BY

MASTER

ADDRESS BYTE

MOST SIGNIFICANT BYTE

ACK

BY

MASTER

*THIS BIT MUST BE 0 IN THE 6-PIN SOT-23 VERSION.

Figure 28. AD5311 Readback Sequence

SCL

SDA

SCL

SDA

D7

D6

D5

D4

D3

D2

D1

D0

X

X

PD1

PD0

D11

D10

D9

D8

000

1

1

A1*

A0

R/

W

NO ACK

BY

MASTER

STOP

COND

BY

MASTER

LEAST SIGNIFICANT BYTE

ACK

BY

AD5321

START

COND

BY

MASTER

ADDRESS BYTE

MOST SIGNIFICANT BYTE

ACK

BY

MASTER

*THIS BIT MUST BE 0 IN THE 6-PIN SOT-23 VERSION.

Figure 29. AD5321 Readback Sequence

of the eight data bits in the DAC register. However, in the

case of the AD5311 and AD5321, the readback consists of two

bytes that contain both the data and the power-down mode bits.

The read operations for the three DACs are shown in the figures

below.