REV. 0

AD5301/AD5311/AD5321

–11–

SCL

SDA

SCL

SDA

D3

D2

D1

D0

XXXX

X

X

PD1

PD0

D7

D6

D5

D4

00

0

1

1

A1*

A0

R/

W

ACK

BY

AD5301

STOP

COND

BY

MASTER

LEAST SIGNIFICANT CONTROL BYTE

ACK

BY

AD5301

START

COND

BY

MASTER

ADDRESS BYTE

MOST SIGNIFICANT CONTROL BYTE

ACK

BY

AD5301

*THIS BIT MUST BE 0 IN THE 6-PIN SOT-23 VERSION.

Figure 24. AD5301 Write Sequence

SCL

SDA

SCL

SDA

D5

D4

D3

D2

D1

D0

X

X

X

X

PD1

PD0

D9

D8

D7

D6

0

0

0

1

1

A1*

A0

R/

W

ACK

BY

AD5311

STOP

COND

BY

MASTER

LEAST SIGNIFICANT CONTROL BYTE

ACK

BY

AD5311

START

COND

BY

MASTER

ADDRESS

BYTE

MOST SIGNIFICANT CONTROL BYTE

ACK

BY

AD5311

*THIS BIT MUST BE 0 IN THE 6-PIN SOT-23 VERSION.

Figure 25. AD5311 Write Sequence

SCL

SDA

SCL

SDA

D7

D6

D5

D4

D3

D2

D1

D0

X

X

PD1

PD0

D11

D10

D9

D8

0

0

0

1

1

A1*

A0

R/

W

ACK

BY

AD5321

STOP

COND

BY

MASTER

LEAST SIGNIFICANT CONTROL BYTE

ACK

BY

AD5321

START

COND

BY

MASTER

ADDRESS BYTE

MOST SIGNIFICANT CONTROL BYTE

ACK

BY

AD5321

*THIS BIT MUST BE 0 IN THE 6-PIN SOT-23 VERSION.

Figure 26. AD5321 Write Sequence

WRITE OPERATION

When writing to the AD5301/AD5311/AD5321 DACs, the user

must begin with an address byte, after which the DAC will

acknowledge that it is prepared to receive data by pulling SDA

low. This address byte is followed by the 16-bit word in the

form of two control bytes. The write operations for the three

DACs are shown in the figures below.