RT8113 datasheet(19/21 Pages) RICHTEK

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RT8113

DS8113-02 April 2011

www.richtek.com

fLC, and place fZ2 at fLC. fP2 is usually placed at fESR to

cancel the ESR zero. And fP3 is placed below switching

frequency to cancel high frequency noise.

For given bandwith, R2, fZ1, fZ2, fP2, fP3, then

MOD@BW

C1 =

2 x f

x R2

C3 =

2 x f x R2

R1 =

2 x f

x C3

R3 =

2 x f

x C3

C2 =

2 x f

x C1 x R2 -1

Thermal Considerations

For continuous operation, do not exceed absolute

maximum junction temperature. The maximum power

dissipation depends on the thermal resistance of IC

package, PCB layout, rate of surrounding airflow and

temperature difference between junction to ambient. The

maximum power dissipation can be calculated by following

the formula :

PD(MAX) = (TJ(MAX)

− TA ) / θJA

where TJ(MAX) is the maximum junction temperature, TA is

the ambient temperature and

θJAis the junction to ambient

thermal resistance.

For recommended operating conditions specification of

the RT8113, the maximum junction temperature is 125

°C

and TA is the ambient temperature. The junction to ambient

thermal resistance

θJA is layout dependent. For

WQFN-24L 4x4 packages, the thermal resistance

θJA is

°C/W on the standard JEDEC 51-7 four-layer thermal

test board. The maximum power dissipation at TA = 25

°C

can be calculated by the following formula :

PD(MAX) = (125

°C − 25°C) / (52°C/W) = 1.923W for

WQFN-24L 4x4 package

The maximum power dissipation depends on operating

ambient temperature for fixed TJ (MAX) and thermal

resistance

θJA. For RT8113 package, the derating curve

in Figure 11 allows the designer to see the effect of rising

ambient temperature on the maximum power dissipation.

Layout Considerations

For best performance of the RT8113, the following

guidelines must be strictly followed :

The power components should be placed first. Keep

the connection between power components as short as

possible.

The shape of the phase plane (the connection plane

between high side MOSFETs, low-side MOSFETs and

output inductors) has to be as square as possible. Long

traces, thin bars or separated islands must be avoided

in the phase plane.

Keep snubber circuits or damping elements near its

objects. Phase RC snubbers have to be close to low-

side MOSFETs, UGATE damping resistor has to be

close to high-side MOSFETs, and boot to phase damping

resistor has to be close to high-side MOSFETs and

phase plane. Also, keep the traces of these snubber

circuits as short as possible.

The area of VIN plane (power stage 12V VIN) and VOUT

plane (output bulk capacitors and inductor connection

plane) has to be as wide as possible. Long traces or

thin bars must be avoided in these planes. The plane

trace width must be wide enough to carry large input/

output current (40mm/A).

The following traces have to be wide and short : UGATE,

LGATE, BOOT, PHASE, and VCC12. Make sure the

widths of these traces are wide enough to carry large

driving current (at least 40mm).

Figure 11. Derating Curves for RT8113 Package

0.00

0.25

0.50

0.75

1.00

1.25

1.50

1.75

2.00

025

100

125

Ambient Temperature (°C)

Four-Layer PCB

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