RT8113 datasheet(12/21 Pages) RICHTEK

12 / 21 page

RT8113

DS8113-02 April 2011

www.richtek.com

Applications Information

The RT8113 is a single-phase synchronous buck DC/DC

converter with embedded MOSFET driver. The internal

VID DAC is designed to interface with the Intel 7-bit

VR11.X compatible VID table for Ibexpeak platform CPU’s

AXG VR application.

Supply voltage, VCC5 regulation and POR

There are two supply voltage pins built-in in the RT8113,

VCC12 and VCC5. VCC12 is a power input pin which

receives external 12V voltage for embedded driver logic

operation. VCC5 is a power output pin which is the output

of an internal 5V LDO regulator. The mentioned 5V LDO

regulator regulates VCC12 to generate a 5V voltage

source for internal gate logic and external circuit biasing,

e.g., OCP biasing. Since the VCC5 voltage is regulated,

the variation of VCC5 (2%) will be much smaller than

Platform ATX +5V (5%~7%). The maximum supply current

of VCC5 is 10mA, which is designed only for controller

circuit biasing. The recommended configuration of the

RT8113 supply voltages is as follows: Platform ATX +12V

to the VCC12 pin, and decoupling capacitors on the

VCC12 and VCC5 pins (minimum 0.1

μF).

The initialization of the RT8113 requires both the voltage

on the VCC12 and VCC5 to be ready. Since VCC5 is

regulated internally from VCC12, the VCC5 voltage will

be ready (>4.6V) after VCC12 reaches about 7V, so there

is no power sequence problem between VCC12 and

VCC5. After VCC5 > 4.6V and VCC12 > 9.6V, the internal

power-on-reset (POR) signal goes high. This POR signal

indicates the power supply voltages are all ready and

initiates soft-start sequence. When POR = low, The

RT8113 will try to turn off both high-side and low-side

MOSFETs to prevent catastrophic failure.

CMP

4.6V

9.6V

VCC12

VCC5

POR

POR : Power ON Reset

Figure 1. Circuit for Power Ready Detection

Switching Frequency

The switching frequency of the RT8113 is set by an external

resistor connected from the RT/EN pin either to GND or to

VCC5. If the resistor is connected from RT/EN to GND,

the load line function will be enabled as well. More details

will be described in the Load Line section. The frequency

follows the graph in Figure 2.

Figure 2. Switching Frequency vs. RRT Resistance

Chip Enable

The enable function of the RT8113 is combined in the

RT/EN pin. Besides frequency setting function, pulling the

RT/EN pin to GND can also force the RT8113 to enter soft

shutdown sequence. It is recommended to connect a

control switch from the RT/EN pin to GND in parallel with

RT setting resistors. The RT8113 will enter soft shutdown

sequence when the control switch is turned on.

Soft-Start

The VOUT soft-start slew rate is set by a capacitor from

the SS pin to FBRTN. Before power on reset (POR =

low), the SS pin is held at GND. After power on reset

(POR = high) and an extra delay of 1600

μs (tD1), the

controller initiates ramping up. VOUT will always trace VEAP

during normal operation of the RT8113, where VEAP is the

positive input of compensation error amplifier, which can

be described as VEAP = VDAC

− VADJ (The definition of VADJ

will be described later in the Load Line section). The first

ramping up duration of VOUT (tD2) ramps VOUT to VBOOT.

200

400

600

800

1000

10203040

50607080

RRT (kΩ)

RT8113 датащи(PDF) 12 Page - Richtek Technology Corporation

RT8113 датащи(HTML) 12 Page - Richtek Technology Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21

датащи скачать

ссылки URL