RT8113 datasheet(18/21 Pages) RICHTEK

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RT8113

DS8113-02 April 2011

www.richtek.com

Figure 9. Compensation Circuit

1) Modulator Characteristic

The modulator consists of the PWM comparator and power

stage. The PWM comparator compares error amplifier EA

output (COMP) with oscillator (OSC) sawtooth wave to

provide a pulse-width modulated (PWM) gate-driving

signal. The PWM wave is smoothed out by the output

filter, LOUT and COUT. The output voltage (VOUT) is sensed

and fed to the inverting input of the error amplifier.

The modulator transfer function is the small-signal transfer

function of VOUT/VCOMP (output voltage over the error

amplifier output). This transfer function is dominated by a

DC gain, a double pole, and an ESR zero as shown in

Figure 10.

The DC gain of the modulator is the input voltage (VIN)

divided by the peak-to-peak oscillator voltage VOSC. The

output LC filter introduces a double pole, 40dB/decade

gain slope above its corner resonant frequency, and a total

phase lag of 180 degrees. The resonant frequency of the

LC filter is expressed as :

OUT

2 x L

x C

The ESR zero is contributed by the ESR associated with

the output capacitance. Note that this requires the output

capacitor to have enough ESR to satisfy stability

requirements. The ESR zero of the output capacitor is

expressed as the following equation :

ESR

OUT

2 x C

x ESR

Figure 10. Bode PLot of Loop Gain

2) Design the compensator

A well-designed compensator regulates the output voltage

to the reference voltage VREF with fast transient response

and good stability. In order to achieve fast transient

response and accurate output regulation, an adequate

compensator design is necessary. The goal of the

compensation network is to provide adequate phase

margin (usually greater than 45

°C) and the highest

bandwidth (0dB crossing frequency, fC) possible. It is also

recommended to manipulate loop frequency response that

its gain crosses over 0dB at a slope of -20dB/dec.

According to Figure 10, the location of poles and zeros

are :

()

f =

2 x R2 x C1

f =

2 x R1 + R3 x C3

f = 0

f =

2 x C3 x R3

f =

C1 x C2 x R2

2 x

C1 + C2

Generally, fZ1 and fZ2 are designed to cancel the double

pole of modulation. Usually, place fZ1 at a fraction of the

fP3

fP2

fZ2

fZ1

LOG

Frequency

fLC

fESR fC

Modulator Gain

Compensation Gain

Closed Loop Gain

OSC

ΔVOSC

ZFB

ZIN

VIN

Driver

REF

PWM

Comparator

COMP

REF

ZFB

ZIN

VOUT

COMP

ESR

COUT

VOUT

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