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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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WM8523GEFL/V датащи(PDF) 24 Page - Wolfson Microelectronics plc |
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WM8523GEFL/V датащи(HTML) 24 Page - Wolfson Microelectronics plc |
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24 / 51 page  WM8523 Production Data w PD, Rev 4.1, August 2011 24 Figure 22 DSP Mode Audio Interface (mode B, AIF_LRCLK_INV=1, Slave) DIGITAL AUDIO INTERFACE CONTROL The control of the audio interface in software mode is achieved by register write. Dynamically changing the audio data format may cause erroneous operation and is not recommended. Digital audio data is transferred to the WM8523 via the digital audio interface. The DAC operates in master or slave mode. The DAC audio interface requires left/right frame clock (LRCLK) and bit clock (BCLK). These can be supplied externally (slave mode) or they can be generated internally (master mode). Selection of master and slave mode is achieved by setting AIF_MSTR bit in Register 3. The frequency of LRCLK in master mode is dependent upon the DAC master clock frequency and the AIF_SR[2:0] bits. The frequency of BCLK in master mode can be selected by AIF_BCLKDIV[2:0]. In slave mode, the MCLK to LRCLK ratio can be auto-detected or set manually using the AIF_SR[2:0] bits. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R3 AIF_CTRL1 03h 7 AIF_MSTR 0 Master/Slave Select 0 = Slave 1 = Master R4 AIF_CTRL2 04h 2:0 AIF_SR[2:0 000 MCLK:LRCLK Ratio 000 = Auto detect 001 = 128fs 010 = 192fs 011 = 256fs 100 = 384fs 101 = 512fs 110 = 768fs 111 = 1152fs 5:3 AIF_BCLK DIV[2:0] 000 BCLK Divider Control (Master Mode) 000 = MCLK/4 001 = MCLK/8 010 = 32fs 011 = 64fs 100 = 128fs 101 - 111 reserved Table 9 DAC Clocking Mode Control |
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