Production Data

WM8523

w

PD, Rev 4.1, August 2011

33

POWER UP AND DOWN CONTROL IN HARDWARE MODE

In hardware mode the MCLK, BCLK and MUTE

¯¯¯¯¯ pins are monitored to control how the device powers up

or down, and this is summarised in Figure 25 below.

Figure 25 Hardware Power Sequence Diagram

Off to Enable

To power up the device to enabled, start MCLK and BCLK and set MUTE

¯¯¯¯¯ = 1.

Off to Standby

To power up the device to standby, start MCLK and BCLK and set MUTE

¯¯¯¯¯ = 0. Once the device is in

standby mode, BCLK can be disabled and the device will remain in standby mode.

Standby to Enable

To transition from the standby state to the enabled state, set the MUTE

¯¯¯¯¯ pin to logic 1 and start BCLK.

Enable to Standby

To power down to a standby state leaving the charge pump running, either set the MUTE

¯¯¯¯¯ pin to logic 0 or

stop BCLK. MCLK must continue to run in these situations. The device will automatically mute and

power down quietly in either case.

Note: It is recommended that the device is placed in standby mode before sample rate change if the sample rate changes more than once

in 1026 LRCLK periods, as detailed in Digital Audio Data Sampling Rates on page 26.

Enable to Off

To power down the device completely, stop MCLK at any time. It is recommended that the device is

placed into standby mode as described above before stopping MCLK to allow a quiet shutdown.

For the timing of the off state to enabled state transition (power on to audio out timing), and the enabled

state to standby state transition (the shutdown timing), please refer to WTN0302.