S29CD032J datasheet(49/81 Pages) SPANSION

49 / 81 page

October 11, 2012 S29CD-J_CL-J_00_B7

S29CD-J and S29CL-J Flash Family

Data

She e t

9.6

Hardware Data Protection Methods

The device offers several methods of data protection by which intended or accidental erasure of any sectors

can be prevented via hardware means. The following subsections describe these methods.

9.6.1

WP# Method

The Write Protect feature provides a hardware method of protecting the two outermost sectors of the large

bank.

If the system asserts VIL on the WP# pin, the device disables program and erase functions in the two

“outermost” boot sectors (8-Kbyte sectors) in the large bank. If the system asserts VIH on the WP# pin, the

device reverts to whether the boot sectors were last set to be protected or unprotected. That is, sector

protection or unprotection for these sectors depends on whether they were last protected or unprotected.

Note that the WP# pin must not be left floating or unconnected as inconsistent behavior of the device may

result.

The WP# pin must be held stable during a command sequence execution

9.6.2

Low VCC Write Inhibit

When VCC is less than VLKO, the device does not accept any write cycles. This protects data during VCC

power-up and power-down.

The command register and all internal program/erase circuits are disabled, and the device resets to reading

array data. Subsequent writes are ignored until VCC is greater than VLKO. The system must provide the

proper signals to the control inputs to prevent unintentional writes when VCC is greater than VLKO.

9.6.3

Write Pulse “Glitch Protection”

Noise pulses of less than 5 ns (typical) on OE#, CE# or WE# do not initiate a write cycle.

9.6.4

Power-Up Write Inhibit

If WE# = CE# = RESET# = VIL and OE# = VIH during power-up, the device does not accept commands on the

rising edge of WE#. The internal state machine is automatically reset to the read mode on power-up.

9.6.5

VCC and VIO Power-up And Power-down Sequencing

The device imposes no restrictions on VCC and VIO power-up or power-down sequencing. Asserting RESET#

to VIL is required during the entire VCC and VIO power sequence until the respective supplies reach the

operating voltages. Once VCC and VIO attain the operating voltages, deassertion of RESET# to VIH is

permitted. Refer to timing in VCC and VIO Power-up on page 57.

9.6.6

Logical Inhibit

Write cycles are inhibited by holding any one of OE# = VIL, CE# = VIH, or WE# = VIH. To initiate a write cycle,

CE# and WE# must be a logical zero (VIL) while OE# is a logical one (VIH).

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