S29CD032J datasheet(39/81 Pages) SPANSION

39 / 81 page

October 11, 2012 S29CD-J_CL-J_00_B7

S29CD-J and S29CL-J Flash Family

Data

She e t

8.8.2

DQ6: Toggle Bit I

Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm is in progress or complete,

or whether the device has entered the Erase Suspend mode.

Toggle Bit I may be read at any address in the same bank, and is valid after the rising edge of the final WE#

pulse in the command sequence (prior to the program or erase operation), and during the sector erase time-

out.

During an Embedded Program or Erase algorithm operation, two immediate consecutive read cycles to any

address cause DQ6 to toggle. When the operation is complete, DQ6 stops toggling. For asynchronous mode,

either OE# or CE# can be used to control the read cycles. For synchronous mode, the rising edge of ADV# is

used or the rising edge of clock while ADV# is Low.

After an erase command sequence is written, if all sectors selected for erasing are protected, DQ6 toggles for

approximately 100 µs, then returns to reading array data. If not all selected sectors are protected, the

Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are

protected.

The system can use DQ6 and DQ2 together to determine whether a sector is actively erasing or is erase-

suspended. When the device is actively erasing (that is, the Embedded Erase algorithm is in progress), DQ6

toggles. When the device enters the Erase Suspend mode, DQ6 stops toggling. However, the system must

also use DQ2 to determine which sectors are erasing or erase-suspended. Alternatively, the system can use

DQ7 (see the subsection on DQ7: Data# Polling).

If a program address falls within a protected sector, DQ6 toggles for approximately 1 µs after the program

command sequence is written, then returns to reading array data.

DQ6 also toggles during the erase-suspend-program mode, and stops toggling once the Embedded Program

Algorithm is complete.

See Figure 18.12, Toggle Bit Timings (During Embedded Algorithms) on page 66 for additional information.

8.8.3

DQ2: Toggle Bit II

The “Toggle Bit II” on DQ2, when used with DQ6, indicates whether a particular sector is actively erasing (that

is, the Embedded Erase algorithm is in progress), or whether that sector is erase-suspended. Toggle Bit II is

valid after the rising edge of the final WE# pulse in the command sequence. DQ2 toggles when the system

performs two consecutive reads at addresses within those sectors that have been selected for erasure. But

DQ2 cannot distinguish whether the sector is actively erasing or is erase-suspended. DQ6, by comparison,

indicates whether the device is actively erasing, or is in Erase Suspend, but cannot distinguish which sectors

are selected for erasure. Thus, both status bits are required for sector and mode information. Refer to

Table 8.8 to compare outputs for DQ2 and DQ6. See DQ6: Toggle Bit I on page 39 for additional information.

S29CD032J датащи(PDF) 39 Page - SPANSION