TPS65708

SLVSAE1A

– OCTOBER 2010 – REVISED FEBRUARY 2011

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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

ORDERING INFORMATION

SIZE FOR WCSP

PACKAGE

PACKAGE

OPTIONS

PACKAGE

VERSION

CODE

MARKING

VDCDC1 = 3.3V

VDCDC2 = 1.8V

VLDO1 = 2.8V

D = 2076

µm ±25 µm

–40°C to 85°C

TPS65708

VLDO2 = 1.2V

YZH

WCSP

TPS65708

E = 2076

µm ±25 µm

ISINK(PWM=1) = 7.5mA

SEQUENCING : DCDC1,

LDO1, DCDC2, LDO2

(1)

For the most current package and ordering information, see the Package Option Addendum at the end of this document, or visit the

device product folder on ti.com, (http://www.ti.com)

ABSOLUTE MAXIMUM RATINGS

Over operating free-air temperature range (unless otherwise noted).

(1)

VALUE

UNIT

MIN

MAX

all pins except A/PGND pins with respect to

–0.3

7

V

AGND

Voltage range

pin VLDO1 and VLDO2 with respect to AGND

–0.3

3.6

V

L1, L2, VLDO1, VLDO2, PGND

700mA

mA

Current

AGND, ISINK

50mA

mA

all other pins

3mA

mA

–40

85

°C

125

°C

–65

150

°C

(1)

Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating

conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

THERMAL INFORMATION

TPS65708

UNITS

YZH (16 Pins)

Junction-to-ambient thermal resistance

75

Junction-to-case (top) thermal resistance

22

Junction-to-board thermal resistance

26

°C/W

Junction-to-top characterization parameter

0.2

Junction-to-board characterization parameter

24

Junction-to-case (bottom) thermal resistance

N/A

(1)

For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

2

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