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AFE5808A датащи(PDF) 63 Page - Texas Instruments |
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AFE5808A датащи(HTML) 63 Page - Texas Instruments |
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63 / 66 page ![]() AFE5808A www.ti.com SLOS729B – OCTOBER 2011 – REVISED APRIL 2012 REVISION HISTORY Changes from Original (October 2011) to Revision A Page • Moved footnote "Low Noise Mode/Medium Power Mode/Low Power Mode" to the test condition for Input Referred Current Noise ........................................................................................................................................................................ 6 • Changed CW signal carrier freq From 8 MHz Max To 8 MHz typical .................................................................................. 8 • Changed CW Clock freq, 4X CLK From 32 MHz Max To 32 MHz typical ........................................................................... 8 • Added footnote for CW Operation Range ............................................................................................................................. 8 • Added text to the ADC Register Map section ..................................................................................................................... 27 • Added text to the CW Clock Selection section ................................................................................................................... 57 • Added text to the Power Management Priority section ....................................................................................................... 59 Changes from Revision A (November 2011) to Revision B Page • Added pin compatible device AFE5803 to the Description text ............................................................................................ 2 • Changed the PIN FUNCTIONS Descriptions ....................................................................................................................... 4 • Changed the tdelay Test Condiitons From: Input clock rising edge (zero cross) to frame clock rising edge (zero cross) minus half the input clock period (T). To: Input clock rising edge (zero cross) to frame clock rising edge (zero cross) minus 3/7 of the input clock period (T). .............................................................................................................................. 22 • Changed the CHANNEL_OFFSET_SUBSTRACTION_ENABLE: Address: 3[8] text ........................................................ 30 • Added Note: 59[8] is only effective in TGC test mode. ....................................................................................................... 34 • Changed Figure 70 ............................................................................................................................................................. 41 • Changed Figure 83 ............................................................................................................................................................. 48 • Changed the TEST MODES section .................................................................................................................................. 60 Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback 63 Product Folder Link(s): AFE5808A |
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