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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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CY29972AXIT датащи(PDF) 1 Page - Cypress Semiconductor |
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CY29972AXIT датащи(HTML) 1 Page - Cypress Semiconductor |
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1 / 13 page  CY29972 3.3 V, 125-MHz Multi-Output Zero Delay Buffer Cypress Semiconductor Corporation • 198 Champion Court • San Jose , CA 95134-1709 • 408-943-2600 Document #: 38-07290 Rev. *E Revised October 11, 2011 3.3 V, 125-MHz Multi-Output Zero Delay Buffer Features ■ Output frequency up to 125 MHz ■ 12 Clock outputs: frequency configurable ■ 350 ps max. output-to-output skew ■ Configurable output disable ■ Two reference clock inputs for dynamic toggling ■ Oscillator or crystal reference input ■ Spread-spectrum-compatible ■ Glitch-free output clocks transitioning ■ 3.3 V power supply ■ Pin-compatible with MPC972 ■ Industrial temperature range: –40 °C to +85 °C ■ 52-pin thin quad flat package (TQFP) package Table 1. Frequency Table [1] VC0_SEL FB_SEL2 FB_SEL1 FB_SEL0 FVC0 0 000 8x 0 001 12x 0 010 16x 0 011 20x 0 100 16x 0 101 24x 0 110 32x 0 111 40x 1 000 4x 1 001 6x 1 010 8x 1 011 10x 1 100 8x 1 101 12x 1 110 16x 1 111 20x Block Diagram REF_SEL 0 1 0 1 Phase Detector VCO LPF Sync Frz D Q QA0 Sync Frz D Q Sync Frz D Q Sync Frz D Q Sync Frz D Q Sync Frz D Q 0 1 /2 Power-On Reset Output Disable Circuitry Data Generator /4, /6, /8, /12 /4, /6, /8, /10 /2, /4, /6, /8 /4, /6, /8, /10 Sync Pulse XIN XOUT TCLK0 TCLK1 TCLK_SEL FB_IN FB_SEL2 MR#/OE SELA(0,1) 2 SELB(0,1) 2 SELC(0,1) 2 FB_SEL(0,1) 2 SCLK SDATA INV_CLK QA1 QA2 QA3 QB0 QB1 QB2 QB3 QC0 QC1 QC2 QC3 FB_OUT SYNC 12 VCO_SEL PLL_EN Note 1. x = the reference input frequency, 200 MHz < FVCO < 480 MHz. [+] Feedback |
Аналогичный номер детали - CY29972AXIT |
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Аналогичное описание - CY29972AXIT |
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