CY29972

Document #: 38-07290 Rev. *E

Page 7 of 13

Power Management

The individual output enable/freeze control of the CY29972

allows the user to implement unique power management

schemes into the design. The outputs are stopped in the logic ‘0’

state when the freeze control bits are activated. The serial input

register contains one programmable freeze enable bit for 12 of

the 14 output clocks. The QC0 and FB_OUT outputs can not be

frozen with the serial port, this avoids any potential lock up

situation should an error occur in the loading of the serial data.

An output is frozen when a logic ‘0’ is programmed and enabled

when a logic ‘1’ is written. The enabling and freezing of individual

outputs is done in such a manner as to eliminate the possibility

of partial “runt” clocks.

The serial input register is programmed through the SDATA input

by writing a logic ‘0’ start bit followed by 12 NRZ freeze enable

bits. The period of each SDATA bit equals the period of the free

running SCLK signal. The SDATA is sampled on the rising edge

of SCLK.

Absolute Maximum Ratings

Exceeding maximum ratings [5] may shorten the useful life of the

device. User guidelines are not tested.

Storage temperature ................................ –65 °C to +150 °C

Operating temperature .............................. –40 °C to +85 °C

Maximum ESD protection .............................................. 2 kV

Maximum power supply ................................................ 5.5 V

Maximum input current ............................................. ±20 mA

This device contains circuitry to protect the inputs against

damage due to high static voltages or electric field; however,

precautions should be taken to avoid application of any voltage

higher than the maximum rated voltages to this circuit. For proper

D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11

D0-D3 are the control bits for QA0-QA3, respectively

D4-D7 are the control bits for QB0-QB3, respectively

D8-D10 are the control bits for QC1-QC3, respectively

D11 is the control bit for SYNC

Start

Bit

Table 3. Suggested Oscillator Crystal Parameters

Parameter

Characteristic

Min

Typ

Max

Unit

Conditions

Frequency tolerance

–

–

±100

ppm Note 3

Frequency temperature stability

–

–

±100

Aging

–

–

5

ppm/

Yr

(first 3 years at 25 °C) [3]

Load capacitance

–

20

–

pF

The crystal’s rated load [3]

Effective series resistance (ESR)

–

40

80

ohms Note 4

Notes

3. For best performance and accurate frequencies from this device, It is recommended but not mandatory that the chosen crystal meet or exceed these specifications.

4. Larger values may cause this device to exhibit oscillator start-up problems.

5. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is not required.

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