CY29972

Document #: 38-07290 Rev. *E

Page 8 of 13

DC Parameters

Parameter

Description

Test Conditions

Min

Typ

Max

Unit

Input Low voltage

–0.8

V

Input High voltage

2.0

–

V

Input Low current [6]

–

–

–120

µA

Input High current

–

–

10

µA

Output Low voltage [7]

–

–

0.5

V

Output High voltage [7]

2.4

–

–

V

Quiescent supply current

–

10

15

mA

PLL supply current

–

15

20

mA

Dynamic supply current

–

225

–

mA

–

125

–

Input pin capacitance

–

4

–

pF

AC Parameters

Parameter [8]

Description

Conditions

Min

Typ

Max

Unit

–

–

3.0

ns

Reference input frequency

Note 9

–

Note 9

MHz

Crystal Oscillator Frequency

see Table 3 on page 7

10

–

25

MHz

Reference input duty cycle

25

–

75

%

PLL VCO lock range

200

–

480

MHz

Maximum PLL lock time

–

–

10

ms

Output clocks rise / fall time [10]

0.8 V to 2.0 V

0.15

–

1.2

ns

Maximum Output Frequency

Q (³2)

–

–

125

MHz

Q (³4)

–

–

120

Q (³6)

–

–

80

Q (³8)

–

–

60

Output duty cycle [10]

–

Output enable time [10] (all outputs)

2

–

10

ns

Output disable time [10] (all outputs)

2

–

8

ns

Cycle to cycle jitter [10] (peak to peak)

–

±

100

–

ps

Any output to any output skew [10, 11]

–250

350

ps

Propagation delay [11, 12]

QFB = (³8)

–270

130

530

ps

–330

70

470

Notes

6. Inputs have pull-up/pull-down resistors that effect input current.

7. Driving series or parallel terminated 50

8. Parameters are guaranteed by design and characterization. Not 100% tested in production.

9. Maximum and minimum input reference is limited by VC0 lock range.

10. Outputs loaded with 30 pF each.

11. 50

12. Tpd is specified for a 50-MHz input reference. Tpd does not include jitter.

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