CY29972

Document #: 38-07290 Rev. *E

Page 4 of 13

Pin Description

Pin [2]

Name

PWR

I/O

Type

Description

11

–I–

Oscillator input. Connect to a crystal.

12

–O–

Oscillator output. Connect to a crystal.

–I

PU

External reference/test clock input.

10

–I

PU

External reference/test clock input.

44, 46, 48, 50

QA(3:0)

O–

Clock outputs. See Table 2 on page 5 for frequency selections.

32, 34, 36, 38

QB(3:0)

O–

Clock outputs. See Table 2 on page 5 for frequency selections.

16, 18, 21, 23

QC(3:0)

O–

Clock outputs. See Table 2 on page 5 for frequency selections.

29

FB_OUT

O–

Feedback clock output. Connect to FB_IN for normal operation. The divider

ratio for this output is set by FB_SEL(0:2). See Table 1 on page 1. A bypass

delay capacitor at this output will control Input Reference/ Output Banks phase

relationships.

25

SYNC

O–

Synchronous pulse output. This output is used for system synchronization.

The rising edge of the output pulse is in sync with both the rising edges of

QA(0:3) and QC(0:3) output clocks regardless of the divider ratios selected.

42, 43

SELA(1,0)

–

I

PU

Frequency select inputs. These inputs select the divider ratio at QA(0:3)

outputs. See Table 2 on page 5.

40, 41

SELB(1,0)

–

I

PU

Frequency select inputs. These inputs select the divider ratio at QB(0:3)

outputs. See Table 2 on page 5.

19, 20

SELC(1,0)

–

I

PU

Frequency select inputs. These inputs select the divider ratio at QC(0:3)

outputs. See Table 2 on page 5.

5, 26, 27

FB_SEL(2:0)

–

I

PU

Feedback select inputs. These inputs select the divide ratio at FB_OUT

output. See Table 1 on page 1.

52

VCO_SEL

–

I

PU

VCO divider select input. When set LOW, the VCO output is divided by 2.

When set HIGH, the divider is bypassed. See Table 1 on page 1.

31

FB_IN

–

I

PU

Feedback clock input. Connect to FB_OUT for accessing the PLL.

6

PLL_EN

–

I

PU

PLL enable input. When asserted HIGH, PLL is enabled; when LOW, PLL is

bypassed.

7

REF_SEL

–

I

PU

Reference select input. When HIGH, the crystal oscillator is selected; when

LOW, TCLK (0,1) is the reference clock.

8

TCLK_SEL

–

I

PU

TCLK select input. When LOW, TCLK0 is selected and when HIGH TCLK1

is selected.

2

MR#/OE

–

I

PU

Master reset/output enable input. When asserted LOW, resets all of the

internal flip-flops and also disables all of the outputs. When pulled high,

releases the internal flip-flops from reset and enables all of the outputs.

14

INV_CLK

–

I

PU

Inverted clock input. When set HIGH, QC(2,3) outputs are inverted. When

set LOW, the inverter is bypassed.

–I

PU

Serial clock input. Clocks data at SDATA into the internal register.

–I

PU

Serial data input. Input data is clocked to the internal register to enable/disable

individual outputs. This provides flexibility in power management.

17, 22, 28,

33,37, 45, 49

–

–

–

3.3 V power supply for output clock buffers.

13

–

–

–

3.3 V power supply for PLL.

1, 15, 24, 30,

35, 39, 47, 51

–

–

–

Common ground.

Note

2. A bypass capacitor (0.1 mF) should be placed as close as possible to each positive power (< 0.2”). If these bypass capacitors are not close to the pins, their

high-frequency filtering characteristics will be cancelled by the lead inductance of the traces.

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