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Freescale Semiconductor, Inc.

MMA685x

3.1.6

Device Configuration Register (DEVCFG)

The device configuration register is a read/write register which contains data for general device configuration. The register can

be written during initialization but is locked once the ENDINIT bit is set. This register is included in the writable register CRC

check. Refer to Section 3.2.2 for details.

3.1.6.1

Reserved Bits (Reserved)

Bits 6 and 7 of the DEVCFG register are reserved. A write to the reserved bits must always be logic ‘0’ for normal device op-

eration and performance.

3.1.6.2

End of Initialization Bit (ENDINIT)

The ENDINIT bit is a control bit used to indicate that the user has completed all device and system level initialization tests,

and that MMA685x will operate in normal mode. Once the ENDINIT bit is set, writes to all writable register bits are inhibited except

for the DEVCTL register. Once written, the ENDINIT bit can only be cleared by a device reset. The writable register CRC check

(reference Section 3.2.2) is only enabled when the ENDINIT bit is set.

3.1.6.3

SD Bit

The SD bit determines the format of acceleration data results. If the SD bit is set to a logic ‘1’, unsigned results are transmitted,

with the zero-g level represented by a nominal value of 512. If the SD bit is cleared, signed results are transmitted, with the zero-

g level represented by a nominal value of 0.

3.1.6.4

OFMON Bit

The OFMON bit determines if the offset monitor circuit is enabled. If the OFMON bit is set to a logic ‘1’, the offset monitor is

enabled. Refer to Section 3.8.5 for more information. If the OFMON bit is cleared, the offset monitor is disabled.

Table 8. Device Configuration Register

Location

Bit

Address

Register

7

6543210

$0B

DEVCFG

Reserved

Reserved

ENDINIT

SD

OFMON

A_CFG[2]

A_CFG[1]

A_CFG[0]

Reset Value

0

0000000

SD

Operating Mode

1

Unsigned Data Output

0

Signed Data Output

OFMON

Operating Mode

1

Offset Monitor Circuit Enabled

0

Offset Monitor Circuit Disabled