Sensors

48

Freescale Semiconductor, Inc.

MMA685x

4.5.3.2

Invalid Register Request

The following conditions result in an “Invalid Register Request” error:

• An attempt is made to write to an un-writable register (Writable registers are defined in Section 3.1, Table 3).

Attempts to write to registers $0D, $0F, $11, and $13 will also result in an error.

• An attempt is made to write to a register while the ENDINIT bit in the DEVCFG register is set

– This applies to all registers with the exception of the DEVCTL register

• An attempt is made to read an un-readable register (Readable registers are defined in Section 3.1, Table 3).

Attempts to read registers $07, $0D, $0F, $11, and $13 will also result in an error.

MMA685x responds to an Invalid Register Request” error with an “Invalid Register Request” response as shown in Table 27.

4.5.4

Device Reset Indications

If the DEVINIT, or DEVRES bit is set in the DEVSTAT register as described in Section 3.1.10, MMA685x will respond to ac-

celeration data requests with an “Internal Error Present” response until the bits are cleared in the DEVSTAT register. The DEVINIT

a read of the DEVSTAT register. The arming function will not be updated on Acceleration Data Request commands if the DEVINIT

or DEVRES bit is set in the DEVSTAT register. The PCM output is disabled if the DEVINIT or DEVRES bit is set.

4.5.5

Internal Error

The following errors will result in an internal error, and set the IDE bit in the DEVSTAT register:

• OTP CRC Failure

• Writable Register CRC Failure

• Self-Test Error

• Invalid internal logic states

4.5.5.1

CRC Error

If the IDE bit is set in the DEVSTAT register due to an OTP Shadow Register or Writable Register CRC failure as described in

Section 3.2, MMA685x will respond to acceleration data requests with an “Internal Error Present” response until the IDE bit is

cleared in the DEVSTAT register. The arming function will not be updated on Acceleration Data Request commands if a CRC

Error is detected. The PCM output is not affected by the CRC error.

If the CRC error is in the writable register array, and the ENDINIT bit in the DEVCFG register has been set, the error can only

be cleared by a device reset. The IDE bit will not be cleared on a read of the DEVSTAT register.

If the CRC error is in the OTP shadow register array, the error cannot be cleared.

Register operations will be executed as specified in Section 4.4.

4.5.5.2

Self-Test Error

If the IDE bit is set in the DEVSTAT register due to a Self-Test activation failure, MMA685x will respond to acceleration data

requests with a “Self-Test Error” response until the IDE bit is cleared in the DEVSTAT register. The arming function will not be

updated on Acceleration Data Request commands if a Self-Test Error is detected. The PCM output is not affected by the Self-

Test Error. The IDE bit in the DEVSTAT register will remain set until a read of the DEVSTAT register occurs, even if the internal

failure is removed. If the internal error is still present when the DEVSTAT register is read, the IDE bit will remain set.

Register operations will be executed as specified in Section 4.4.

4.5.6

Offset Monitor Over Range

If an offset monitor over range is present as described in Section 3.8.5, MMA685x will respond to an acceleration request with

a “Valid Acceleration Data Request” response, but the Status bits (S[1:0]) will be set to ‘10’. The arming function will be updated

on Acceleration Data Request commands even if an Offset Monitor Over Range is detected. Once the over range condition is

removed, MMA685x will respond to acceleration requests with a “Valid Acceleration Data Request” response with the Status bits

(S[1:0]) set to ‘10’ on the next SPI transfer, and a “Valid Acceleration Data Request” response with normal status on subsequent

SPI transfers. The OFF bit in the DEVSTAT register will remain set until a read of the DEVSTAT register occurs.

The PCM output is not affected by the offset monitor over range condition.

Register operations will be executed as specified in Section 4.4.