MMA685X datasheet(9/52 Pages) FREESCALE

9 / 52 page

Sensors

Freescale Semiconductor, Inc.

MMA685x

2.6

Dynamic Electrical Characteristics - Supply and SPI

VL ≤ (VCC - VSS) ≤ VH, TL ≤ TA ≤ TH, |ΔTA| < 25 K/min unless otherwise specified

Parameters tested 100% at final test.

Parameters tested 100% at wafer probe.

Parameters verified by characterization

(*) Indicates a critical characteristic.

Verified by qualification testing.

Parameters verified by pass/fail testing in production.

Functionality guaranteed by modeling, simulation and/or design verification. Circuit integrity assured through IDDQ and scan testing. Timing is deter-

mined by internal system clock frequency.

N/A

Devices are trimmed at 100 Hz with 1000 Hz low-pass filter option selected. Response is corrected to 0 Hz response.

10. Low-pass filter cutoff frequencies shown are -3dB referenced to 0 Hz response.

11. Power supply ripple at frequencies greater than 900 kHz should be minimized to the greatest extent possible.

12. Time from falling edge of CS to ARM output valid.

13. N/A

14. Thermal resistance between the die junction and the exposed pad; cold plate is attached to the exposed pad.

15. Device characterized at all values of VL and VH. Production test is conducted at all typical voltages (VTYP) unless otherwise noted.

16. Data path Latency is the signal latency from g-cell to SPI output disregarding filter group delays.

17. Filter characteristics are specified independently, and do not include g-cell frequency response.

18. Electrostatic Deflection Test completed during wafer probe.

19. Verified by simulation.

20. Acceleration Data Request timing constraint only applies for proper operation of the Arming Function.

Characteristic

Symbol

Min

Typ

Max

Units

129

130

Power-On Recovery Time (VCC = VCCMIN to first SPI access)

Power-On Recovery Time (Internal POR to first SPI access)

tOP

⎯

840

μs

(3)

(3, 7)

131

132

Internal Oscillator Frequency

Test Frequency - Divided from Internal Oscillator

fOSC

fOSCTST

7.6

0.95

8.4

1.05

MHz

(7)

(1)

133

134

135

136

137

138

139

140

141

142

143

144

145

146

147

148

Serial Interface Timing (See Figure 6, CMISO ≤ 80 pF, RMISO ≥ 10 kΩ)

Clock (SCLK) period (10% of VCC to 10% of VCC)

Clock (SCLK) high time (90% of VCC to 90% of VCC)

Clock (SCLK) low time (10% of VCC to 10% of VCC)

Clock (SCLK) rise time (10% of VCC to 90% of VCC)

Clock (SCLK) fall time (90% of VCC to 10% of VCC)

CS asserted to SCLK high (CS = 10% of VCC to SCLK = 10% of VCC)

CS asserted to MISO valid (CS = 10% of VCC to MISO = 10/90% of VCC)

Data setup time (MOSI = 10/90% of VCC to SCLK = 10% of VCC)

MOSI Data hold time (SCLK = 90% of VCC to MOSI = 10/90% of VCC)

MISO Data hold time (SCLK = 90% of VCC to MISO = 10/90% of VCC)

SCLK low to data valid (SCLK = 10% of VCC to MISO = 10/90% of VCC)

SCLK low to CS high (SCLK = 10% of VCC to CS = 90% of VCC)

CS high to MISO disable (CS = 90% of VCC to MISO = Hi Z)

CS high to CS low (CS = 90% of VCC to CS = 90% of VCC)

SCLK low to CS low (SCLK = 10% of VCC to CS = 90% of VCC)

CS high to SCLK high (CS = 90% of VCC to SCLK = 90% of VCC)

tSCLK

tSCLKH

tSCLKL

tSCLKR

tSCLKF

tLEAD

tACCESS

tSETUP

tHOLD_IN

tHOLD_OUT

tVALID

tLAG

tDISABLE

tCSN

tCLKCS

tCSCLK

120

⎯

526

⎯

(3)

(19)

(3)

(19)

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