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LTC3104 датащи(PDF) 20 Page - Linear Technology |
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LTC3104 датащи(HTML) 20 Page - Linear Technology |
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20 / 26 page ![]() LTC3630 20 3630fb Pin Clearance/Creepage Considerations The LTC3630 is available in two packages (MSE16 and DHC) both with identical functionality. However, the 0.2mm (minimum space) between pins and paddle on the DHC- package may not provide sufficient PC board trace clearance between high and low voltage pins in some higher voltage applications. In applications where clearance is required, APPLICATIONS INFORMATION VFB ISET SW L1 33μH VIN RUN FBO COUT 100μF 2 CIN 4.7μF CISET 100pF RISET 220k CIN: TDK C5750X7R2A-475M (2220) COUT: 2 AVX 1812D107MAT L1: SUMIDA CDRH105RNP-330N VOUT 5V 500mA VIN 5V TO 65V 3630 F13 SS VPRG1 VPRG2 GND LTC3630 Figure 13. 5V to 65V Input to 5V Output, High Efficiency, 500mA Regulator VFB ISET SW L1 VIN RUN R3 R1 R2 CIN COUT VOUT VIN R4 RISET CISET CSS 3630 F12 FBO SS VPRG2 VPRG1 LTC3630 VIAS TO GROUND PLANE OUTLINE OF LOCAL GROUND PLANE VOUT VIN GND GND L1 COUT CIN Figure 12. Example PCB Layout the MSE16 package should be used. The MSE16 package has removed pins between all the adjacent high voltage and low voltage pins, providing 0.657mm clearance which will be sufficient for most applications. For more informa- tion, refer to the printed circuit board design standards described in IPC-2221 (www.ipc.org). |
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