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LTC3630

3630fb

APPLICATIONS INFORMATION

The value of CIN is selected to keep the input from droop-

ing less than 240mV (1%):

CIN >

10μH • 1.2A2

2 • 24V • 240mV

≅ 2.2μF

COUT will be selected based on a value large enough to

satisfy the output voltage ripple requirement. For a 50mV

output ripple, the value of the output capacitor can be

calculated from:

COUT >

10μH • 1.2A2

2 • 3.3V • 50mV

≅ 47μF

COUT also needs an ESR that will satisfy the output voltage

ripple requirement. The required ESR can be calculated

from:

ESR

50mV

1.2A

≅ 40mΩ

A 47μF ceramic capacitor has significantly less ESR than

40mΩ.

Since an output voltage of 3.3V is one of the standard

output configurations, the LTC3630 can be configured

by connecting VPRG1 to ground and VPRG2 to the SS pin.

The undervoltage lockout requirement on VIN can be satis-

fied with a resistive divider from VIN to the RUN pin (refer

to Figure 9). Calculate R3 and R4 as follows:

= 200k whichis ≤

12V

40μA

200k • 1.21V

12V – 1.21V

+200k • 4μA

= 20.9k

Choose standard values for R3 = 200k, R4 = 21k. Note

that the VIN falling threshold will be 10% less than the

rising threshold or 11V.

Since the maximum VIN is more than 4.5x the UVLO thresh-

old, a 4.7V Zener diode in parallel with R4 is required to

keep the maximum voltage on the RUN pin less than the

absolute maximum of 6V.

VFB

10μH

VIN

RUN

200k

2.2μF

47μF

VOUT

3.3V

500mA

VIN

24V

21k

4.7V

3630 F11

VPRG2

VPRG1

FBO

ISET

GND

LTC3630

Figure 11. 24V to 3.3V, 500mA Regulator at 200kHz

The ISET pin should be left open in this example to select

maximum peak current (1.2A typical). Figure 11 shows a

complete schematic for this design example.

PC Board Layout Checklist

When laying out the printed circuit board, the following

checklist should be used to ensure proper operation of

the LTC3630. Check the following in your layout:

1. Large switched currents flow in the power switches

and input capacitor. The loop formed by these compo-

nents should be as small as possible. A ground plane

is recommended to minimize ground impedance.

2. Connect the (+) terminal of the input capacitor, CIN, as

close as possible to the VIN pin. This capacitor provides

the AC current into the internal power MOSFETs.

3. Keep the switching node, SW, away from all sensitive

small signal nodes. The rapid transitions on the switching

node can couple to high impedance nodes, in particular

VFB, and create increased output ripple.

4. Flood all unused area on all layers with copper except

for the area under the inductor. Flooding with copper

will reduce the temperature rise of power components.

You can connect the copper areas to any DC net (VIN,

VOUT, GND, or any other DC rail in your system).

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