SC5010

32

Definition of Registers and Bits (continued)

Analog Dimming Control Register

This register is used to program the LED string current through the on-chip 5-bit DAC.

Bit Field

Definition

Read / Write Description

0x02 [4:0]

IDAC [4:0]

R / W

5-bit analog dimming register — The LED string current can be evenly adjusted in 32 steps

from 0mA to the maximum value determined by R

ISET

.

For example, if the maximum LED string current set by R

ISET

is 20mA/string, when IDAC[4:0] is

Dimming Duty Cycle Control Register

These two registers (0x03 and 0x04) combine together as a 10-bit register for controlling the PWM dimming duty

cycle.

Bit Field

Definition

Read / Write Description

0x03 [1:0]

0x04 [7:0]

D [9:0]

R / W

10-bit PWM brightness setting — This value is spread over registers: 0x03 (MSB) and 0x04

(LSB). The LED PWM dimming duty cycle can be evenly adjusted by the 10-bit register from 0

to 100% with D[9:0] value changes from 0 to 0x3F.

Dimming Frequency Select Register

This register is used to program the LED PWM dimming frequency.

Bit Field

Definition

Read / Write Description

0x05 [7:0]

FREQ [7:0]

R / W

This register sets the LED dimming frequency.

FAST_FREQ = 1, then LED dimming frequency is equal to 10MHz / (512 x (FREQ+1))

FAST_FREQ = 0, then LED dimming frequency is equal to 10MHz / (1024 x (FREQ+1))

PLL Control Registers

This register is used to set the PLL divider value.

Bit Field

Definition

Read / Write Description

0x06 [1:0]

0x07 [7:0]

0x08 [7:0]

NPLL [17:0]

R / W

These registers set the PLL divider value — The system clock is intended to run at 10MHz; this

value divides the system clock down to a frequency comparable to the SYNC signal’s frequen-

cy to allow PLL synchronization. Typical values are shown below.

F

IN

PLL Divider N

Register Values

FPLL = (N+2) × F

IN

60 Hz

169,982

0x02 - 0x97 - 0xFE

10MHz

1 MHz

8

10MHz