SC5010 datasheet(31/36 Pages) SEMTECH

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SC5010

Device Control Register

This register provides different control features of the device.

Bit Field

Definition

Read / Write Description

0x01 [7:6]

WIN[1:0]

R/W

A modified duty cycle sent into the PWMI pin replaces the existing saved duty cycle when its

deviation from the saved duty is outside the window for two consecutive samples.

00 = 0 bits (no window)

01 = ±1 bit window

10 = ±2 bit window

11 = ±3 bit window

0x01 [5]

FAST_FREQ

R/W

Determines the LED PWM dimming frequency selection:

0 = Low PWM dimming frequency mode assuming 10-bit PWM duty cycle dimming, dividing

the system clock 10MHz / (1024 x (FREQ+1)).

1 = High PWM dimming frequency mode assuming 9-bit PWM duty cycle dimming, dividing

the system clock 10MHz / (512 x (FREQ+1)).

0x01 [4]

FLT_EN

R/W

This bit enables fault checking:

0 = LED_OPEN and LED_SHORT faults are not checked.

1 = LED_OPEN and LED_SHORT faults are checked.

0x01 [3]

SYNC_EN

R/W

Enables video signal synchronization with the PLL:

0 = SYNC is disabled.

1 = PLL tracks the SYNC input signal.

0x01 [2]

PH_SHIFT

R/W

Enables String-by-String phase shifting. This is a don’t care if INT_PWM=0.

0 = Phase shifting disabled.

1 = Phase shifting is enabled

0x01 [1]

INT_DUTY

R/W

Determines the duty cycle source. This is a don’t care if INT_PWM = 0.

0 = LED duty cycle is set by the PWMI input

1 = LED duty cycle is set by the 10-bit duty cycle control registers

0x01 [0]

INT_PWM

R/W

Sets the LED PWM dimming source.

0 = LED PWM dimming driven directly from the PWMI input source (direct PWM dimming)

1 = LED PWM dimming driven from an internal oscillator (required for phase-shifted PWM

dimming); enables the PLL.

Definition of Registers and Bits (continued)

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