MPC5125 datasheet(48/94 Pages) FREESCALE

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MPC5125 Microcontroller Data Sheet, Rev. 4

Electrical and Thermal Characteristics

Freescale Semiconductor

1. The SYS_XTAL_IN frequency, Sys PLL, and Core PLL settings must be chosen so that the resulting e300 clk, csb_clk, and

MCK frequencies do not exceed their respective maximum or minimum operating frequencies.

2. The values are valid for the user-operation mode. There can be deviations for test modes.

3. When selecting the peripheral clock frequencies, care needs to be taken about requirements for baud rates and minimum

frequency limitation.

4.The DDR data rate is 2x the DDR memory bus frequency.



SYS_XTAL_IN is the input clock multiplied by the system phase-locked loop (Sys PLL) and the clock unit to create the coherent

system bus clock (csb_clk), the internal clock for the DDR controller (ddr_clk), and the clocks for the peripherals.The csb_clk

serves as the clock input to the e300 core. A second PLL inside the e300 core multiplies the csb_clk frequency to create the

internal clock for the e300 core (core_clk). The system and core PLL multipliers are selected by the SPMF and COREPLL fields

in the reset configuration word, which is loaded at power-on reset.



See the MPC5125 Reference Manual (MPC5125RM)

, for more information on the clock subsystem.

4.3.3

Resets

The MPC5125 has three reset pins:

•

PORESET — Power-on reset

•HRESET — Hard reset

•SRESET — Software reset

These signals are asynchronous I/O signals and can be asserted at any time. The input side uses a Schmitt trigger and requires

the same input characteristics as other MPC5125 inputs, as specified in Section 4.1, “DC Electrical Characteristics.”

As long as VDD is not stable the HRESET output is not stable.

The timing relationship can be seen in the following figures.

Table 18. Reset Rise / Fall Timing

Description

Min

Max

Unit

SpecID

PORESET1 fall time

NOTES:

1 Make sure that the PORESET does not carry any glitches. The MPC5125 has no

filter to prevent them from getting into the chip.

—1

A3.4

PORESET rise time

—

A3.5

HRESET2,3 fall time

2 HRESET and SRESET must have a monotonous rise time.

3 The assertion of HRESET becomes active at power-on reset without any

SYS_XTAL clock.

—1

A3.6

HRESET rise time

—

A3.7

SRESET fall time

—

A3.8

SRESET rise time

—

A3.9

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