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MPC5125 датащи(PDF) 34 Page - Freescale Semiconductor, Inc |
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MPC5125 датащи(HTML) 34 Page - Freescale Semiconductor, Inc |
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34 / 94 page ![]() HRESET —ALT0 ALT1 ALT2 ALT3 HRESET — — — — — — I — — — VDD_IO 1. This pin is an input or open-drain output, and have internal pull-up P-FETs. This pin can not be configured. 5. This pin contains an enabled internal schmitt-trigger. A17 PORESET —ALT0 ALT1 ALT2 ALT3 PORESET — — — — — — I — — — VDD_IO 1. This pin is an input or open-drain output, and have internal pull-up P-FETs. This pin can not be configured. 2. This pin is an input only. This pin cannot be configured. 5. This pin contains an enabled internal schmitt-trigger. C17 SRESET —ALT0 ALT1 ALT2 ALT3 SRESET — — — — — — I — — — VDD_IO 1. This pin is an input or open-drain output, and have internal pull-up P-FETs. This pin can not be configured. 5. This pin contains an enabled internal schmitt-trigger. A18 Test/Debug TEST — ALT0 ALT1 ALT2 ALT3 TEST — — — — — — I — — — VDD_IO 2. This pin is an input only. This pin cannot be configured. 4. This test pin must be tied to VSS. D14 Table 2. MPC5125 Pin Multiplexing (continued) Pin Pad I/O Control Register1 and Offset2 Alternate Function3 Functions4 Peripheral5 I/O Direction Power Domain Notes Pin |
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