Rev. 1.00

16

November 22, 2011

HT16C21

Acknowledge

● Each bytes of eight bits is followed by one acknowledge bit. This acknowledge bit is a low level placed on the

● A slave receiver which is addressed must generate an acknowledge, ACK, after the reception of each byte.

● The device that acknowledges must pull down the SDA line during the acknowledge clock pulse so that it

remains stable low during the high period of this clock pulse.

● A master receiver must signal an end of data to the slave by generating a not-acknowledge, NACK, bit on the

last byte that has been clocked out of the slave. In this case, the master receiver must leave the data line high

during the 9th pulse to not acknowledge. The master will generate a STOP or repeated START condition.

S

1

2

7

8

9

clock pulse for

acknowledgement

Data Output

by Transmitter

Data Outptu

by Receiver

SCL From

Master

acknowledge

not acknowledge

START

condition

Slave Addressing

● The slave address byte is the first byte received following the START condition form the master device. The

first seven bits of the first byte make up the slave address. The eighth bit defines a read or write operation to be

performed. When the R/W bit is “1”, then a read operation is selected. A “0” selects a write operation.

● The HT16C21 address bits are “0111000”. When an address byte is sent, the device compares the first seven

bits after the START condition. If they match, the device outputs an Acknowledge on the SDA line.

Slave Address

0

1

1

1

0

0

0

R/W

MSB

LSB